clkmgr Simulation Results

Simulation Results: clkmgr

10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
80.43 %

code
79.47 %

assert
93.80 %

func
68.02 %

line
91.48 %

branch
94.01 %

cond
87.07 %

toggle
99.81 %

FSM
25.00 %

Validation stages

V1		50.00%
V2		68.42%
V2S		58.82%
V3		0.00%

4/8 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	clkmgr_smoke	1.020s	24.456us	1	1	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	0.890s	37.593us	1	1	100.00
csr_rw				0	1	0.00
	clkmgr_csr_rw	0.750s	6.292us	0	1	0.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	0.570s	2.256us	0	1	0.00
csr_aliasing				1	1	100.00
	clkmgr_csr_aliasing	3.050s	331.846us	1	1	100.00
csr_mem_rw_with_rand_reset				0	1	0.00
	clkmgr_csr_mem_rw_with_rand_reset	1.250s	70.489us	0	1	0.00
regwen_csr_and_corresponding_lockable_csr				1	2	50.00
	clkmgr_csr_rw	0.750s	6.292us	0	1	0.00
	clkmgr_csr_aliasing	3.050s	331.846us	1	1	100.00

13/19 passed

68.42 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				1	1	100.00
	clkmgr_peri	0.890s	14.062us	1	1	100.00
trans_enables				1	1	100.00
	clkmgr_trans	2.060s	132.087us	1	1	100.00
clk_status				1	1	100.00
	clkmgr_clk_status	0.880s	24.240us	1	1	100.00
jitter				1	1	100.00
	clkmgr_smoke	1.020s	24.456us	1	1	100.00
frequency				1	1	100.00
	clkmgr_frequency	0.960s	28.883us	1	1	100.00
frequency_timeout				0	1	0.00
	clkmgr_frequency_timeout	1.150s	46.658us	0	1	0.00
frequency_overflow				1	1	100.00
	clkmgr_frequency	0.960s	28.883us	1	1	100.00
stress_all				0	1	0.00
	clkmgr_stress_all	3.180s	296.904us	0	1	0.00
alert_test				1	1	100.00
	clkmgr_alert_test	1.050s	43.834us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	clkmgr_tl_errors	5.760s	560.713us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	clkmgr_tl_errors	5.760s	560.713us	1	1	100.00
tl_d_outstanding_access				2	4	50.00
	clkmgr_csr_hw_reset	0.890s	37.593us	1	1	100.00
	clkmgr_csr_rw	0.750s	6.292us	0	1	0.00
	clkmgr_csr_aliasing	3.050s	331.846us	1	1	100.00
	clkmgr_same_csr_outstanding	0.720s	3.541us	0	1	0.00
tl_d_partial_access				2	4	50.00
	clkmgr_csr_hw_reset	0.890s	37.593us	1	1	100.00
	clkmgr_csr_rw	0.750s	6.292us	0	1	0.00
	clkmgr_csr_aliasing	3.050s	331.846us	1	1	100.00
	clkmgr_same_csr_outstanding	0.720s	3.541us	0	1	0.00

V2S

10/17 passed

58.82 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				1	2	50.00
	clkmgr_sec_cm	4.400s	475.504us	1	1	100.00
	clkmgr_tl_intg_err	0.740s	15.020us	0	1	0.00
shadow_reg_update_error				1	1	100.00
	clkmgr_shadow_reg_errors	1.220s	67.323us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	clkmgr_shadow_reg_errors	1.220s	67.323us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	clkmgr_shadow_reg_errors	1.220s	67.323us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	clkmgr_shadow_reg_errors	1.220s	67.323us	1	1	100.00
shadow_reg_update_error_with_csr_rw				0	1	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	0.950s	37.866us	0	1	0.00
sec_cm_bus_integrity				0	1	0.00
	clkmgr_tl_intg_err	0.740s	15.020us	0	1	0.00
sec_cm_meas_clk_bkgn_chk				1	1	100.00
	clkmgr_frequency	0.960s	28.883us	1	1	100.00
sec_cm_timeout_clk_bkgn_chk				0	1	0.00
	clkmgr_frequency_timeout	1.150s	46.658us	0	1	0.00
sec_cm_meas_config_shadow				1	1	100.00
	clkmgr_shadow_reg_errors	1.220s	67.323us	1	1	100.00
sec_cm_idle_intersig_mubi				1	1	100.00
	clkmgr_idle_intersig_mubi	1.190s	66.782us	1	1	100.00
sec_cm_jitter_config_mubi				0	1	0.00
	clkmgr_csr_rw	0.750s	6.292us	0	1	0.00
sec_cm_idle_ctr_redun				1	1	100.00
	clkmgr_sec_cm	4.400s	475.504us	1	1	100.00
sec_cm_meas_config_regwen				0	1	0.00
	clkmgr_csr_rw	0.750s	6.292us	0	1	0.00
sec_cm_clk_ctrl_config_regwen				0	1	0.00
	clkmgr_csr_rw	0.750s	6.292us	0	1	0.00
prim_count_check				1	1	100.00
	clkmgr_sec_cm	4.400s	475.504us	1	1	100.00

0/2 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
regwen				1
	clkmgr_regwen	0.640s	6.900us	1
stress_all_with_rand_reset				1
	clkmgr_stress_all_with_rand_reset	1.940s	70.600us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b
	clkmgr_frequency_timeout	87964713445655586210682123721956124960477121055308601387381378011408671681475	75	UVM_ERROR @ 46657767 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00 UVM_INFO @ 46657767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	35491840777884993395841728258287155469077329879520882671125819793196556957404	177	UVM_ERROR @ 70600111 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00 UVM_INFO @ 70600111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	31986037000469069795723516442666921789293170873917087781620547269160694069752	226	UVM_ERROR @ 296903575 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00 UVM_INFO @ 296903575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en
	clkmgr_regwen	50974527759161963760796044878988058601754063986984150252770912994467714472025	71	UVM_ERROR @ 6899788 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en UVM_INFO @ 6899788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:
	clkmgr_shadow_reg_errors_with_csr_rw	39359006662418622898171675496798622622603371390592499433161355347428904145279	72	UVM_ERROR @ 37866138 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 UVM_INFO @ 37866138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	37835643664727334170567141166240223903113482528719389930710006760270762002579	104	UVM_ERROR @ 15019837 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 UVM_INFO @ 15019837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	47815290819382745014541520505638232267563914737557630387559932156722975172847	72	UVM_ERROR @ 6292175 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 UVM_INFO @ 6292175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:
	clkmgr_csr_bit_bash	33624651229765461122734488958658235148673971927515191381665504888206716436903	72	UVM_ERROR @ 2256450 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0 UVM_INFO @ 2256450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:642) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch
	clkmgr_same_csr_outstanding	16977061662565672017036605343804711890570971812496717758385719342397102595333	72	UVM_ERROR @ 3541311 ps: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xf7efb164 read out mismatch UVM_INFO @ 3541311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:
	clkmgr_csr_mem_rw_with_rand_reset	68159497331823541222476188188199141855512710424112587055015793804300927856464	79	UVM_ERROR @ 70488629 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 UVM_INFO @ 70488629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---