Simulation Results: dma

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.50 %
  • code
  • 91.47 %
  • assert
  • 95.55 %
  • func
  • 60.47 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 90.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 7.000s 295.552us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 6.000s 829.088us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 445.169us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 52.535us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 129.602us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 12.000s 5915.514us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 770.368us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 25.146us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 129.602us 1 1 100.00
dma_csr_aliasing 4.000s 770.368us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 120.000s 20781.981us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 139.000s 14112.454us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 208.000s 89922.254us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 208.000s 89922.254us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 139.000s 14112.454us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 196.000s 68722.851us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 208.000s 89922.254us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 11.000s 2899.128us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 122.000s 35572.932us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 39.981us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 14.682us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 56.436us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 56.436us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 52.535us 1 1 100.00
dma_csr_rw 2.000s 129.602us 1 1 100.00
dma_csr_aliasing 4.000s 770.368us 1 1 100.00
dma_same_csr_outstanding 1.000s 175.239us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 52.535us 1 1 100.00
dma_csr_rw 2.000s 129.602us 1 1 100.00
dma_csr_aliasing 4.000s 770.368us 1 1 100.00
dma_same_csr_outstanding 1.000s 175.239us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 12.000s 103.412us 1 1 100.00
dma_generic_stress 196.000s 68722.851us 1 1 100.00
dma_handshake_stress 208.000s 89922.254us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 928.911us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 1359.750us 1 1 100.00
dma_sec_cm 2.000s 11.837us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 88.000s 11012.134us 1 1 100.00
dma_longer_transfer 4.000s 119.356us 1 1 100.00
dma_stress_all_with_rand_reset 3.000s 103.819us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 61702602243264958246753542018003838436220022773767371690115785535462350639353 88
UVM_ERROR @ 103818742ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 103818742ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---