| V1 |
|
87.50% |
| V2 |
|
52.38% |
| V2S |
|
16.67% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| edn_csr_hw_reset | 0.880s | 159.242us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| edn_csr_rw | 0.780s | 28.707us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| edn_csr_bit_bash | 2.170s | 244.733us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| edn_csr_aliasing | 1.320s | 79.744us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| edn_csr_mem_rw_with_rand_reset | 0.860s | 65.967us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| edn_csr_rw | 0.780s | 28.707us | 1 | 1 | 100.00 | |
| edn_csr_aliasing | 1.320s | 79.744us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| edn_intr_test | 0.880s | 22.709us | 1 | 1 | 100.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| edn_tl_errors | 2.570s | 114.369us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| edn_tl_errors | 2.570s | 114.369us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| edn_csr_hw_reset | 0.880s | 159.242us | 1 | 1 | 100.00 | |
| edn_csr_rw | 0.780s | 28.707us | 1 | 1 | 100.00 | |
| edn_csr_aliasing | 1.320s | 79.744us | 1 | 1 | 100.00 | |
| edn_same_csr_outstanding | 1.150s | 47.096us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| edn_csr_hw_reset | 0.880s | 159.242us | 1 | 1 | 100.00 | |
| edn_csr_rw | 0.780s | 28.707us | 1 | 1 | 100.00 | |
| edn_csr_aliasing | 1.320s | 79.744us | 1 | 1 | 100.00 | |
| edn_same_csr_outstanding | 1.150s | 47.096us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 1 | 2 | 50.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_tl_intg_err | 1.280s | 263.964us | 1 | 1 | 100.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 1 | 1 | 100.00 | |||
| edn_tl_intg_err | 1.280s | 263.964us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Error-[P1ARGS-CANTOPN-F] Cannot open file | ||||
| default | None | 253 |
Error-[P1ARGS-CANTOPN-F] Cannot open file
Unable to open
'/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/lowrisc_dv_edn_sim_0.1.scr'
due to 'No such file or directory'.
Please fix the reason mentioned above and continue.
|
|
| Job killed most likely because its dependent job failed. | ||||
| edn_smoke | 91227033222160116550692589043135770471320816685575288233459330586921242051111 | None | ||
| edn_regwen | 113963792854619985410746808791143503611275074231837352328066418812246469551103 | None | ||
| edn_genbits | 96463737647627131280515066896370549935612996093548268767915689316361246256138 | None | ||
| edn_stress_all | 17702353964419807475572679362161761937529651530362254413475107536514880402837 | None | ||
| edn_stress_all_with_rand_reset | 24963618511033795934575239398353125317226155643096530711863100356543104888986 | None | ||
| edn_intr | 93915561325309911094499246560288083174942812854820438710563180752951538386938 | None | ||
| edn_alert | 25360731456091572178235357575822516186666169557013619416235822849460757200619 | None | ||
| edn_err | 88290371536021146460923262950831554062203852405415307191905697926893293872094 | None | ||
| edn_disable | 79708219437648130571837741720666346708276512106789420750049452764024701533393 | None | ||
| edn_disable_auto_req_mode | 9139253103512296725079130554056509189188983685976504413576304692251353414691 | None | ||
| edn_sec_cm | 81856851015069344214283833291172924775528033139498352363245940728655349349310 | None | ||
| edn_alert_test | 10614898865043856078828817260421113109470957700766910324611563657546831972359 | None | ||