| V1 |
|
87.50% |
| V2 |
|
52.38% |
| V2S |
|
16.67% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| edn_csr_hw_reset | 1.130s | 22.552us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| edn_csr_rw | 0.900s | 15.468us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| edn_csr_bit_bash | 2.390s | 463.604us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| edn_csr_aliasing | 0.840s | 17.167us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| edn_csr_mem_rw_with_rand_reset | 0.800s | 73.597us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| edn_csr_rw | 0.900s | 15.468us | 1 | 1 | 100.00 | |
| edn_csr_aliasing | 0.840s | 17.167us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| edn_intr_test | 0.970s | 16.905us | 1 | 1 | 100.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| edn_tl_errors | 2.620s | 178.309us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| edn_tl_errors | 2.620s | 178.309us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| edn_csr_hw_reset | 1.130s | 22.552us | 1 | 1 | 100.00 | |
| edn_csr_rw | 0.900s | 15.468us | 1 | 1 | 100.00 | |
| edn_csr_aliasing | 0.840s | 17.167us | 1 | 1 | 100.00 | |
| edn_same_csr_outstanding | 1.030s | 129.344us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| edn_csr_hw_reset | 1.130s | 22.552us | 1 | 1 | 100.00 | |
| edn_csr_rw | 0.900s | 15.468us | 1 | 1 | 100.00 | |
| edn_csr_aliasing | 0.840s | 17.167us | 1 | 1 | 100.00 | |
| edn_same_csr_outstanding | 1.030s | 129.344us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 1 | 2 | 50.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_tl_intg_err | 1.970s | 178.216us | 1 | 1 | 100.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 1 | 1 | 100.00 | |||
| edn_tl_intg_err | 1.970s | 178.216us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Error-[P1ARGS-CANTOPN-F] Cannot open file | ||||
| default | None | 253 |
Error-[P1ARGS-CANTOPN-F] Cannot open file
Unable to open
'/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/lowrisc_dv_edn_sim_0.1.scr'
due to 'No such file or directory'.
Please fix the reason mentioned above and continue.
|
|
| Job killed most likely because its dependent job failed. | ||||
| edn_smoke | 76547342186092324258412924128998486579486227346357619314145852269441849215639 | None | ||
| edn_regwen | 108480584742003278391644483222488557859150065102408677274724586281471234062727 | None | ||
| edn_genbits | 71672056851036625362839867808261421519851467391485666255276221120005920882935 | None | ||
| edn_stress_all | 42181741338482736849210007915435786709552186321466743871064139527024988502982 | None | ||
| edn_stress_all_with_rand_reset | 34466089775996840479578579472200846177801459275224208231167363424862644568077 | None | ||
| edn_intr | 112657779385033570036548630705352758897884168286331216736379972119704334779278 | None | ||
| edn_alert | 102757000087442047705305718865684770824177244554126421808666901741968855392306 | None | ||
| edn_err | 12789036079934485640793564313012720495911185445969591512172178927389672147203 | None | ||
| edn_disable | 99077700709093397647887023775134085582288407323473608513105351454692842840628 | None | ||
| edn_disable_auto_req_mode | 33686890046729125246237485907903624064982397304091235342027734079377519575775 | None | ||
| edn_sec_cm | 103826531302028560328847949640197925224312479578400540888944959927311361269803 | None | ||
| edn_alert_test | 86470777985604938055134936699172838670726985819138299196256791596525024831084 | None | ||