Simulation Results: hmac

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.92 %
  • code
  • 97.02 %
  • assert
  • 96.42 %
  • func
  • 43.32 %
  • line
  • 99.68 %
  • branch
  • 98.84 %
  • cond
  • 95.39 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.590s 187.024us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.150s 43.648us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.890s 35.791us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.240s 311.276us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.290s 376.637us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.890s 331.043us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.890s 35.791us 1 1 100.00
hmac_csr_aliasing 4.290s 376.637us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 32.260s 839.813us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 23.520s 1290.311us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.500s 655.645us 1 1 100.00
hmac_test_sha384_vectors 377.290s 10769.508us 1 1 100.00
hmac_test_sha512_vectors 21.080s 251.320us 1 1 100.00
hmac_test_hmac256_vectors 7.300s 222.467us 1 1 100.00
hmac_test_hmac384_vectors 10.520s 1569.984us 1 1 100.00
hmac_test_hmac512_vectors 12.330s 438.996us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 3.570s 1777.331us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 549.180s 5084.542us 1 1 100.00
error 1 1 100.00
hmac_error 11.560s 563.659us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 4.650s 218.686us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.590s 187.024us 1 1 100.00
hmac_long_msg 32.260s 839.813us 1 1 100.00
hmac_back_pressure 23.520s 1290.311us 1 1 100.00
hmac_datapath_stress 549.180s 5084.542us 1 1 100.00
hmac_burst_wr 3.570s 1777.331us 1 1 100.00
hmac_stress_all 737.330s 30388.456us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.590s 187.024us 1 1 100.00
hmac_long_msg 32.260s 839.813us 1 1 100.00
hmac_back_pressure 23.520s 1290.311us 1 1 100.00
hmac_datapath_stress 549.180s 5084.542us 1 1 100.00
hmac_wipe_secret 4.650s 218.686us 1 1 100.00
hmac_test_sha256_vectors 8.500s 655.645us 1 1 100.00
hmac_test_sha384_vectors 377.290s 10769.508us 1 1 100.00
hmac_test_sha512_vectors 21.080s 251.320us 1 1 100.00
hmac_test_hmac256_vectors 7.300s 222.467us 1 1 100.00
hmac_test_hmac384_vectors 10.520s 1569.984us 1 1 100.00
hmac_test_hmac512_vectors 12.330s 438.996us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.590s 187.024us 1 1 100.00
hmac_long_msg 32.260s 839.813us 1 1 100.00
hmac_back_pressure 23.520s 1290.311us 1 1 100.00
hmac_datapath_stress 549.180s 5084.542us 1 1 100.00
hmac_burst_wr 3.570s 1777.331us 1 1 100.00
hmac_error 11.560s 563.659us 1 1 100.00
hmac_wipe_secret 4.650s 218.686us 1 1 100.00
hmac_test_sha256_vectors 8.500s 655.645us 1 1 100.00
hmac_test_sha384_vectors 377.290s 10769.508us 1 1 100.00
hmac_test_sha512_vectors 21.080s 251.320us 1 1 100.00
hmac_test_hmac256_vectors 7.300s 222.467us 1 1 100.00
hmac_test_hmac384_vectors 10.520s 1569.984us 1 1 100.00
hmac_test_hmac512_vectors 12.330s 438.996us 1 1 100.00
hmac_stress_all 737.330s 30388.456us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 737.330s 30388.456us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.820s 43.749us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.780s 12.795us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.010s 223.863us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.010s 223.863us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.150s 43.648us 1 1 100.00
hmac_csr_rw 0.890s 35.791us 1 1 100.00
hmac_csr_aliasing 4.290s 376.637us 1 1 100.00
hmac_same_csr_outstanding 1.440s 77.794us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.150s 43.648us 1 1 100.00
hmac_csr_rw 0.890s 35.791us 1 1 100.00
hmac_csr_aliasing 4.290s 376.637us 1 1 100.00
hmac_same_csr_outstanding 1.440s 77.794us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.880s 64.860us 1 1 100.00
hmac_tl_intg_err 2.460s 206.100us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.460s 206.100us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.590s 187.024us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.520s 264.714us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 35.140s 2405.498us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.140s 33.181us 1 1 100.00

Error Messages

   Test seed line log context