Simulation Results: i2c

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.96 %
  • code
  • 81.35 %
  • assert
  • 95.98 %
  • func
  • 80.55 %
  • line
  • 96.38 %
  • branch
  • 92.26 %
  • cond
  • 85.01 %
  • toggle
  • 89.66 %
  • FSM
  • 43.45 %
Validation stages
V1
100.00%
V2
89.80%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 24.400s 3231.625us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 7.630s 4830.685us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.820s 30.828us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.950s 45.586us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.420s 542.552us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.510s 97.393us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.780s 60.663us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.950s 45.586us 1 1 100.00
i2c_csr_aliasing 1.510s 97.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.930s 4.890us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 346.580s 26229.734us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 21.880s 2687.541us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.920s 28.923us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 130.250s 13104.534us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 35.900s 4037.133us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.320s 430.508us 1 1 100.00
i2c_host_fifo_fmt_empty 4.250s 1502.119us 1 1 100.00
i2c_host_fifo_reset_rx 3.110s 153.884us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 134.790s 15471.936us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 13.970s 1648.647us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 2.180s 88.690us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 2.320s 2477.768us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 25.010s 27503.456us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.830s 9978.275us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 32.720s 1377.577us 1 1 100.00
i2c_target_intr_smoke 3.460s 9999.289us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.010s 172.240us 1 1 100.00
i2c_target_fifo_reset_tx 1.330s 491.108us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 33.920s 25081.974us 1 1 100.00
i2c_target_stress_rd 32.720s 1377.577us 1 1 100.00
i2c_target_intr_stress_wr 22.370s 18445.340us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.050s 12597.233us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 1.400s 548.305us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.990s 3136.173us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 18.190s 10072.371us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.000s 348.514us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.340s 330.343us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 21.880s 2687.541us 1 1 100.00
i2c_host_perf_precise 1.440s 639.520us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 13.970s 1648.647us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.000s 129.834us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 3.590s 5818.073us 1 1 100.00
i2c_target_nack_acqfull_addr 1.930s 488.570us 1 1 100.00
i2c_target_nack_txstretch 1.260s 226.712us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 10.540s 710.676us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 2.160s 2372.333us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.830s 42.534us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.970s 28.585us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.860s 199.557us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.860s 199.557us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.820s 30.828us 1 1 100.00
i2c_csr_rw 0.950s 45.586us 1 1 100.00
i2c_csr_aliasing 1.510s 97.393us 1 1 100.00
i2c_same_csr_outstanding 1.070s 88.413us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.820s 30.828us 1 1 100.00
i2c_csr_rw 0.950s 45.586us 1 1 100.00
i2c_csr_aliasing 1.510s 97.393us 1 1 100.00
i2c_same_csr_outstanding 1.070s 88.413us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.370s 198.668us 1 1 100.00
i2c_sec_cm 1.110s 144.158us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.370s 198.668us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 14.630s 3176.361us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.950s 41.063us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 3.810s 257.728us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 97917559477492811543096321739504016488909654891719076980177989391272549138024 83
UVM_ERROR @ 4889799 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 4889799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 17171342191611946080004642361500142941100954091775827673944973077203347527174 129
UVM_ERROR @ 26229733642 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 26229733642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 26697035961719297714566929517657557726221097031051191291582488738926428037102 85
UVM_ERROR @ 257727822 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 257727822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 51601055221492831684396595790037790663149191675807200253503279778182059457474 81
UVM_ERROR @ 2477768304 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 2477768304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*])
i2c_target_unexp_stop 5862502335019164592959949922813356752574387395358248186025409173975604381370 75
UVM_ERROR @ 41063277 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 41063277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 51393573267163948820210247475363557668736145479654082714543354782460857773693 76
UVM_FATAL @ 10072370564 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10072370564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 76253756344349799664174526884789583976096776912680672823824449475728279206675 93
UVM_ERROR @ 3176361399 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3176361399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: *
i2c_target_nack_txstretch 51448972925822269965170348469930216724447505292075037939774208078500552787957 75
UVM_ERROR @ 226712096 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 226712096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---