Simulation Results: keymgr

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.64 %
  • code
  • 95.10 %
  • assert
  • 97.72 %
  • func
  • 64.10 %
  • line
  • 98.74 %
  • branch
  • 97.76 %
  • cond
  • 92.90 %
  • toggle
  • 97.75 %
  • FSM
  • 88.37 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.080s 1017.516us 1 1 100.00
random 1 1 100.00
keymgr_random 6.490s 201.273us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 0.870s 84.052us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.010s 21.955us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 5.490s 568.953us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 9.690s 372.572us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.250s 81.460us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.010s 21.955us 1 1 100.00
keymgr_csr_aliasing 9.690s 372.572us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 8.230s 1534.801us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.280s 214.447us 1 1 100.00
keymgr_sideload_kmac 5.270s 261.261us 1 1 100.00
keymgr_sideload_aes 3.090s 97.539us 1 1 100.00
keymgr_sideload_otbn 2.640s 101.961us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 3.970s 460.576us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 3.330s 113.057us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.880s 102.850us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 18.730s 4022.724us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 1.740s 194.948us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 3.540s 289.054us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 369.150s 49997.862us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.870s 17.116us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.690s 12.339us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.750s 145.350us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.750s 145.350us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 0.870s 84.052us 1 1 100.00
keymgr_csr_rw 1.010s 21.955us 1 1 100.00
keymgr_csr_aliasing 9.690s 372.572us 1 1 100.00
keymgr_same_csr_outstanding 1.750s 52.352us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 0.870s 84.052us 1 1 100.00
keymgr_csr_rw 1.010s 21.955us 1 1 100.00
keymgr_csr_aliasing 9.690s 372.572us 1 1 100.00
keymgr_same_csr_outstanding 1.750s 52.352us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 5.530s 931.157us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 5.530s 931.157us 1 1 100.00
keymgr_tl_intg_err 3.160s 212.460us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.250s 413.620us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.250s 413.620us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.250s 413.620us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.250s 413.620us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 9.920s 4943.245us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 5.530s 931.157us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 5.530s 931.157us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 3.160s 212.460us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.250s 413.620us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 8.230s 1534.801us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 6.490s 201.273us 1 1 100.00
keymgr_csr_rw 1.010s 21.955us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 6.490s 201.273us 1 1 100.00
keymgr_csr_rw 1.010s 21.955us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 6.490s 201.273us 1 1 100.00
keymgr_csr_rw 1.010s 21.955us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 3.330s 113.057us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.740s 194.948us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.740s 194.948us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 6.490s 201.273us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.680s 63.380us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.530s 931.157us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.530s 931.157us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 5.530s 931.157us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 3.980s 640.375us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 3.330s 113.057us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 5.530s 931.157us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.530s 931.157us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 5.530s 931.157us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.980s 640.375us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.980s 640.375us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 5.530s 931.157us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.980s 640.375us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.530s 931.157us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 3.980s 640.375us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 1.630s 103.911us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 26095704399761422205640254588775507871202987442914106693472315501139973061222 104
UVM_ERROR @ 103910740 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 103910740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---