Simulation Results: kmac

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.61 %
  • code
  • 88.56 %
  • assert
  • 95.48 %
  • func
  • 90.79 %
  • line
  • 97.33 %
  • branch
  • 95.41 %
  • cond
  • 93.08 %
  • toggle
  • 99.96 %
  • FSM
  • 57.02 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 40.150s 14205.328us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.950s 54.513us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.990s 27.228us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 10.070s 302.603us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.390s 202.830us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.130s 98.452us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.990s 27.228us 1 1 100.00
kmac_csr_aliasing 3.390s 202.830us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.760s 37.351us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.190s 39.527us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 104.730s 7061.265us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 176.710s 40731.038us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 32.120s 10417.898us 1 1 100.00
kmac_test_vectors_sha3_256 1092.920s 67190.817us 1 1 100.00
kmac_test_vectors_sha3_384 20.640s 434.846us 1 1 100.00
kmac_test_vectors_sha3_512 791.000s 66154.704us 1 1 100.00
kmac_test_vectors_shake_128 1981.830s 106936.188us 1 1 100.00
kmac_test_vectors_shake_256 95.470s 34942.609us 1 1 100.00
kmac_test_vectors_kmac 2.200s 63.942us 1 1 100.00
kmac_test_vectors_kmac_xof 3.050s 1409.759us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 125.610s 6271.284us 1 1 100.00
app 1 1 100.00
kmac_app 142.300s 150022.711us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 82.180s 4155.301us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 139.530s 6773.965us 1 1 100.00
error 1 1 100.00
kmac_error 228.570s 23752.918us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 2.880s 2010.525us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 85.480s 10101.350us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 3.550s 147.960us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 21.340s 1068.403us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 21.930s 7984.513us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.180s 42.798us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 1024.010s 81340.916us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.830s 50.541us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.070s 31.780us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.190s 57.452us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.190s 57.452us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.950s 54.513us 1 1 100.00
kmac_csr_rw 0.990s 27.228us 1 1 100.00
kmac_csr_aliasing 3.390s 202.830us 1 1 100.00
kmac_same_csr_outstanding 1.920s 351.614us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.950s 54.513us 1 1 100.00
kmac_csr_rw 0.990s 27.228us 1 1 100.00
kmac_csr_aliasing 3.390s 202.830us 1 1 100.00
kmac_same_csr_outstanding 1.920s 351.614us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.230s 40.066us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.230s 40.066us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.230s 40.066us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.230s 40.066us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.210s 124.854us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_tl_intg_err 2.400s 277.658us 1 1 100.00
kmac_sec_cm 42.990s 9038.288us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.400s 277.658us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.180s 42.798us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 40.150s 14205.328us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 125.610s 6271.284us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.230s 40.066us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 42.990s 9038.288us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 42.990s 9038.288us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 42.990s 9038.288us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 40.150s 14205.328us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.180s 42.798us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 42.990s 9038.288us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 110.570s 33876.557us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 40.150s 14205.328us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 35.930s 7077.078us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11)
kmac_sideload_invalid 55428769083233440243398892076898091166785032422498726014102423995926394912643 86
UVM_FATAL @ 10101350491 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6de59000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10101350491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---