Simulation Results: lc_ctrl

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.25 %
  • code
  • 88.37 %
  • assert
  • 95.99 %
  • func
  • 89.39 %
  • line
  • 97.64 %
  • branch
  • 96.13 %
  • cond
  • 79.51 %
  • toggle
  • 82.85 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
90.00%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.920s 104.589us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.020s 28.411us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.800s 13.959us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.200s 68.261us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 36.509us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.200s 39.974us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.800s 13.959us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 36.509us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.460s 143.630us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.060s 242.806us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.920s 48.809us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.660s 22.700us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 2.950s 7.913us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.600s 681.162us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 2.950s 7.913us 0 1 0.00
lc_ctrl_prog_failure 1.660s 22.700us 1 1 100.00
lc_ctrl_errors 5.600s 681.162us 1 1 100.00
lc_ctrl_security_escalation 6.510s 543.911us 1 1 100.00
lc_ctrl_jtag_state_failure 3.130s 532.537us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.500s 272.765us 1 1 100.00
lc_ctrl_jtag_errors 31.840s 3251.832us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 1.500s 61.982us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.120s 148.178us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.850s 537.373us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.560s 1041.792us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.430s 186.685us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.680s 182.612us 1 1 100.00
lc_ctrl_jtag_alert_test 1.440s 91.450us 1 1 100.00
lc_ctrl_jtag_smoke 8.010s 1953.472us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.340s 1004.851us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.500s 272.765us 1 1 100.00
lc_ctrl_jtag_errors 31.840s 3251.832us 1 1 100.00
lc_ctrl_jtag_access 6.800s 1684.192us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.900s 1208.250us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.130s 710.165us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.850s 25.006us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 15.190s 13056.435us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.960s 79.807us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.540s 227.139us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.540s 227.139us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 28.411us 1 1 100.00
lc_ctrl_csr_rw 0.800s 13.959us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 36.509us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.890s 57.730us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 28.411us 1 1 100.00
lc_ctrl_csr_rw 0.800s 13.959us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 36.509us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.890s 57.730us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.340s 275.638us 1 1 100.00
lc_ctrl_sec_cm 7.970s 882.309us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.340s 275.638us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.060s 242.806us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 2.950s 7.913us 0 1 0.00
lc_ctrl_sec_cm 7.970s 882.309us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 2.950s 7.913us 0 1 0.00
lc_ctrl_sec_cm 7.970s 882.309us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 2.950s 7.913us 0 1 0.00
lc_ctrl_sec_cm 7.970s 882.309us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 2.950s 7.913us 0 1 0.00
lc_ctrl_sec_cm 7.970s 882.309us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 2.950s 7.913us 0 1 0.00
lc_ctrl_sec_cm 7.970s 882.309us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 2.950s 7.913us 0 1 0.00
lc_ctrl_sec_cm 7.970s 882.309us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 2.950s 7.913us 0 1 0.00
lc_ctrl_sec_cm 7.970s 882.309us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 2.950s 7.913us 0 1 0.00
lc_ctrl_sec_cm 7.970s 882.309us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.510s 543.911us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.460s 143.630us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.340s 1004.851us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.160s 1639.683us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.160s 1639.683us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.480s 799.429us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.750s 4664.588us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.750s 4664.588us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 31.770s 1530.925us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 8142373892947196004008518579689649882310409680690882804763379110852477047707 213
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 7912556 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 7912556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 115348749314101615940659192637514258280454475005236395323560968283060153993128 594
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 532536608 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 532536608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 52866580617391291859491625068929774498591770555811669069169376901720417898143 1433
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 13056435093 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 13056435093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 101593583755199420739584925684555849699887967335013513236071425651751667477189 4283
UVM_ERROR @ 1530924803 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1530924803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---