Simulation Results: lc_ctrl

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.13 %
  • code
  • 86.92 %
  • assert
  • 95.99 %
  • func
  • 90.47 %
  • line
  • 97.77 %
  • branch
  • 96.01 %
  • cond
  • 79.95 %
  • toggle
  • 77.16 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
90.00%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.120s 329.977us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.770s 26.412us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.100s 15.386us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.410s 126.304us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 25.233us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.350s 102.374us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.100s 15.386us 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 25.233us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.600s 62.343us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.750s 316.443us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 101.136us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.130s 48.373us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 2.930s 7.022us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.850s 350.955us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 2.930s 7.022us 0 1 0.00
lc_ctrl_prog_failure 2.130s 48.373us 1 1 100.00
lc_ctrl_errors 5.850s 350.955us 1 1 100.00
lc_ctrl_security_escalation 4.620s 507.016us 1 1 100.00
lc_ctrl_jtag_state_failure 5.580s 460.529us 0 1 0.00
lc_ctrl_jtag_prog_failure 6.530s 1988.800us 1 1 100.00
lc_ctrl_jtag_errors 43.740s 9676.655us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 2.430s 88.265us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.900s 69.357us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.370s 2522.569us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.220s 902.564us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.030s 66.410us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.610s 146.479us 1 1 100.00
lc_ctrl_jtag_alert_test 1.220s 74.416us 1 1 100.00
lc_ctrl_jtag_smoke 2.770s 758.815us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.080s 802.676us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.530s 1988.800us 1 1 100.00
lc_ctrl_jtag_errors 43.740s 9676.655us 1 1 100.00
lc_ctrl_jtag_access 16.410s 2149.766us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.840s 1599.602us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 14.860s 978.489us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.830s 23.551us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 2.390s 71.173us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.130s 22.074us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.280s 290.409us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.280s 290.409us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.770s 26.412us 1 1 100.00
lc_ctrl_csr_rw 1.100s 15.386us 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 25.233us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.850s 18.832us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.770s 26.412us 1 1 100.00
lc_ctrl_csr_rw 1.100s 15.386us 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 25.233us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.850s 18.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 2.010s 53.020us 1 1 100.00
lc_ctrl_sec_cm 6.220s 1083.307us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.010s 53.020us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.750s 316.443us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 2.930s 7.022us 0 1 0.00
lc_ctrl_sec_cm 6.220s 1083.307us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 2.930s 7.022us 0 1 0.00
lc_ctrl_sec_cm 6.220s 1083.307us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 2.930s 7.022us 0 1 0.00
lc_ctrl_sec_cm 6.220s 1083.307us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 2.930s 7.022us 0 1 0.00
lc_ctrl_sec_cm 6.220s 1083.307us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 2.930s 7.022us 0 1 0.00
lc_ctrl_sec_cm 6.220s 1083.307us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 2.930s 7.022us 0 1 0.00
lc_ctrl_sec_cm 6.220s 1083.307us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 2.930s 7.022us 0 1 0.00
lc_ctrl_sec_cm 6.220s 1083.307us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 2.930s 7.022us 0 1 0.00
lc_ctrl_sec_cm 6.220s 1083.307us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.620s 507.016us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.600s 62.343us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.080s 802.676us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.170s 270.869us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.170s 270.869us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.680s 393.935us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.240s 1303.647us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.240s 1303.647us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 2.590s 53.873us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 58718994578978615490665260060379272323517755939380305393337491024046203512238 167
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 7022077 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 7022077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 77973506913078730538803445955397113192482047021062179087513270338626593720046 698
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 460529167 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 460529167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 23333871134742663128233040109734158102916950317838994508023684930933582860409 192
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 71173224 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 71173224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 16231251687121517474528684954933465717208874082167766432715360382866754876144 468
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 53872536 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 53872536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---