Simulation Results: mbx

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.37 %
  • code
  • 91.55 %
  • assert
  • 97.01 %
  • func
  • 85.55 %
  • block
  • 96.68 %
  • line
  • 96.64 %
  • branch
  • 91.89 %
  • toggle
  • 86.12 %
Validation stages
V1
100.00%
V2
87.50%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 42.000s 2397.780us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 32.165us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 28.554us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 2.000s 113.269us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 55.976us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
mbx_csr_mem_rw_with_rand_reset 1.000s 40.596us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 28.554us 1 1 100.00
mbx_csr_aliasing 1.000s 55.976us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 19.000s 10177.837us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 1.000s 4.789us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 27.000s 5498.945us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 7.000s 2563.128us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 52.391us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 55.640us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
mbx_tl_errors 4.000s 138.760us 1 1 100.00
tl_d_illegal_access 1 1 100.00
mbx_tl_errors 4.000s 138.760us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 32.165us 1 1 100.00
mbx_csr_rw 2.000s 28.554us 1 1 100.00
mbx_csr_aliasing 1.000s 55.976us 1 1 100.00
mbx_same_csr_outstanding 1.000s 32.311us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 32.165us 1 1 100.00
mbx_csr_rw 2.000s 28.554us 1 1 100.00
mbx_csr_aliasing 1.000s 55.976us 1 1 100.00
mbx_same_csr_outstanding 1.000s 32.311us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_sec_cm 1.000s 12.653us 1 1 100.00
mbx_tl_intg_err 2.000s 278.397us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_stress 12647102589502025160222932541919946152657782507967190474081160934000125185541 704
UVM_ERROR @ 10177836665 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 10177836665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_stress_zero_delays 103820278390694743435347535610607122033752789462036380570990493935406695400283 86
UVM_ERROR @ 4788683 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 4788683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---