Simulation Results: otbn

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.56 %
  • code
  • 94.87 %
  • assert
  • 88.81 %
  • func
  • 97.01 %
  • block
  • 99.43 %
  • line
  • 99.56 %
  • branch
  • 93.26 %
  • toggle
  • 91.78 %
  • FSM
  • 94.87 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 126.406us 1 1 100.00
single_binary 1 1 100.00
otbn_single 7.000s 139.576us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 13.018us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 21.418us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 425.328us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 99.450us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 6.000s 282.827us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 21.418us 1 1 100.00
otbn_csr_aliasing 4.000s 99.450us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 38.000s 7407.485us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 17.000s 910.586us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 16.000s 252.893us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 41.000s 604.202us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 25.000s 250.455us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 49.000s 391.106us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 10.000s 30.705us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 16.851us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 6.000s 34.868us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 3.000s 71.538us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 57.452us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 210.863us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 210.863us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 13.018us 1 1 100.00
otbn_csr_rw 5.000s 21.418us 1 1 100.00
otbn_csr_aliasing 4.000s 99.450us 1 1 100.00
otbn_same_csr_outstanding 4.000s 65.642us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 13.018us 1 1 100.00
otbn_csr_rw 5.000s 21.418us 1 1 100.00
otbn_csr_aliasing 4.000s 99.450us 1 1 100.00
otbn_same_csr_outstanding 4.000s 65.642us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 5.000s 43.756us 1 1 100.00
otbn_dmem_err 9.000s 27.293us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 6.000s 102.312us 1 1 100.00
otbn_controller_ispr_rdata_err 8.000s 56.309us 1 1 100.00
otbn_mac_bignum_acc_err 6.000s 149.143us 1 1 100.00
otbn_urnd_err 5.000s 18.030us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 8.000s 38.776us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 38.661us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 4.000s 133.223us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_tl_intg_err 8.000s 704.453us 1 1 100.00
otbn_sec_cm 85.000s 1822.156us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 13.000s 133.144us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 85.000s 1822.156us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 85.000s 1822.156us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 126.406us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 9.000s 27.293us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 5.000s 43.756us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 8.000s 704.453us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 10.000s 30.705us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 5.000s 43.756us 1 1 100.00
otbn_dmem_err 9.000s 27.293us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 16.851us 1 1 100.00
otbn_illegal_mem_acc 8.000s 38.776us 1 1 100.00
otbn_sec_cm 85.000s 1822.156us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 85.000s 1822.156us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 7.000s 139.576us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 5.000s 43.756us 1 1 100.00
otbn_dmem_err 9.000s 27.293us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 16.851us 1 1 100.00
otbn_illegal_mem_acc 8.000s 38.776us 1 1 100.00
otbn_sec_cm 85.000s 1822.156us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 85.000s 1822.156us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 10.000s 30.705us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 5.000s 43.756us 1 1 100.00
otbn_dmem_err 9.000s 27.293us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 16.851us 1 1 100.00
otbn_illegal_mem_acc 8.000s 38.776us 1 1 100.00
otbn_sec_cm 85.000s 1822.156us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 85.000s 1822.156us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 7.000s 139.576us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 8.000s 30.618us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 12.129us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 17.000s 577.687us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 17.000s 577.687us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 5.000s 26.601us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 85.000s 1822.156us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 85.000s 1822.156us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 198.441us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 85.000s 1822.156us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 85.000s 1822.156us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 9.000s 68.419us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 9.000s 68.419us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 33.854us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 139.576us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 139.576us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 7.000s 139.576us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 25.000s 250.455us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 7.000s 139.576us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 7.000s 139.576us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 7.000s 22.693us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 7.000s 139.576us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 85.000s 1822.156us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 99.000s 421.274us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 113639328558636899083283213928140884740512895269022050571478453785316239231088 294
UVM_FATAL @ 421273969 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 421273969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---