Simulation Results: otp_ctrl

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.12 %
  • code
  • 71.16 %
  • assert
  • 93.16 %
  • func
  • 55.05 %
  • line
  • 87.52 %
  • branch
  • 84.17 %
  • cond
  • 85.74 %
  • toggle
  • 61.18 %
  • FSM
  • 37.21 %
Validation stages
V1
100.00%
V2
68.00%
V2S
85.71%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.960s 860.584us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 5.420s 269.967us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.010s 80.305us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.070s 168.009us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.920s 358.939us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 6.600s 290.203us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.890s 150.745us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.070s 168.009us 1 1 100.00
otp_ctrl_csr_aliasing 6.600s 290.203us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.090s 538.103us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.520s 166.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 118.090s 4613.971us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.820s 321.458us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 9.210s 558.826us 0 1 0.00
otp_ctrl_check_fail 7.480s 481.589us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 10.300s 4082.153us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 10.800s 1894.161us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 6.680s 348.477us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 16.640s 700.314us 1 1 100.00
otp_ctrl_parallel_lc_esc 2.990s 399.765us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 15.650s 994.804us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 18.820s 586.240us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 5.850s 138.433us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 19.970s 8443.850us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.380s 87.915us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.890s 158.333us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.790s 2315.812us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.790s 2315.812us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.010s 80.305us 1 1 100.00
otp_ctrl_csr_rw 2.070s 168.009us 1 1 100.00
otp_ctrl_csr_aliasing 6.600s 290.203us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.960s 128.046us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.010s 80.305us 1 1 100.00
otp_ctrl_csr_rw 2.070s 168.009us 1 1 100.00
otp_ctrl_csr_aliasing 6.600s 290.203us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.960s 128.046us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_tl_intg_err 23.970s 1609.819us 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 23.970s 1609.819us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 5.420s 269.967us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 5.420s 269.967us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.990s 399.765us 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.990s 399.765us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.990s 399.765us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.990s 399.765us 1 1 100.00
otp_ctrl_macro_errs 18.820s 586.240us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.990s 399.765us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.990s 399.765us 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.990s 399.765us 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.990s 399.765us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.990s 399.765us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.990s 399.765us 1 1 100.00
otp_ctrl_macro_errs 18.820s 586.240us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.990s 399.765us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.990s 399.765us 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.820s 321.458us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 7.480s 481.589us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 10.800s 1894.161us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 10.800s 1894.161us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 10.800s 1894.161us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 10.800s 1894.161us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 10.800s 1894.161us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 5.420s 269.967us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 10.800s 1894.161us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 5.420s 269.967us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 307.110s 25456.616us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 10.300s 4082.153us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 5.420s 269.967us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 5.420s 269.967us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 18.820s 586.240us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 126.120s 59143.885us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.830s 65.553us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *
otp_ctrl_partition_walk 101208425859505104497343466544661518121361693685129374951139279128802614495886 165224
UVM_ERROR @ 4613970704 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 4613970704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 65930930052735970292514565692962966946442467519661533670759281323379933278685 7445
UVM_ERROR @ 4082153053 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 4082153053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 30739128926438692720153968578296989205210399641122795181256546583276877712557 86
UVM_ERROR @ 59143884690 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 59143884690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state
otp_ctrl_background_chks 97107161895445562488381834428341245167404763304281875411042721180663642071685 10973
UVM_ERROR @ 558826477 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 558826477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 64627332225448034289226113859214133059356432431674334263665955121907433167197 7600
UVM_ERROR @ 348477152 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 348477152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_dai_lock 49647670690335526460090326328069420866829210528221873394613002897318330864189 5861
UVM_ERROR @ 1894160728 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 1894160728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 54181817245615757498829128958260747175149272771620877547987757358146383064662 5820
UVM_ERROR @ 138432897 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 138432897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 114729575510830546546336553869940744655668218585114627681324514527818457726846 5235
UVM_ERROR @ 481588711 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3242370241 [0xc142a4c1] vs 3242369217 [0xc142a0c1]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 481588711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 39851202378603655016096095048492514222152341640149591824654374214270989624882 88
UVM_ERROR @ 65553284 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 65553284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1308) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_stress_all 58573783716133619488304300184324933434328680271460797108526654312052970241714 5624
UVM_ERROR @ 8443850248 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 8443850248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---