Simulation Results: rom_ctrl

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.69 %
  • code
  • 96.62 %
  • assert
  • 96.80 %
  • func
  • 96.66 %
  • line
  • 99.32 %
  • branch
  • 98.91 %
  • cond
  • 98.22 %
  • toggle
  • 99.97 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 9.210s 565.927us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.190s 221.698us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.420s 1797.570us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 9.020s 297.761us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.640s 557.528us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.180s 219.738us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.420s 1797.570us 1 1 100.00
rom_ctrl_csr_aliasing 6.640s 557.528us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.910s 1410.336us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.160s 299.409us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 9.120s 313.703us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 25.060s 2855.479us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.230s 3046.040us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.440s 300.651us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.620s 729.398us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.620s 729.398us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.190s 221.698us 1 1 100.00
rom_ctrl_csr_rw 6.420s 1797.570us 1 1 100.00
rom_ctrl_csr_aliasing 6.640s 557.528us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.980s 543.669us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.190s 221.698us 1 1 100.00
rom_ctrl_csr_rw 6.420s 1797.570us 1 1 100.00
rom_ctrl_csr_aliasing 6.640s 557.528us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.980s 543.669us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.460s 1440.134us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.090s 3193.564us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_tl_intg_err 52.260s 372.372us 1 1 100.00
rom_ctrl_sec_cm 486.360s 10430.465us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 486.360s 10430.465us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 486.360s 10430.465us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.460s 1440.134us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.460s 1440.134us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.460s 1440.134us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.460s 1440.134us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.460s 1440.134us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 486.360s 10430.465us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 486.360s 10430.465us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 9.210s 565.927us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 9.210s 565.927us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 9.210s 565.927us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 52.260s 372.372us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.460s 1440.134us 1 1 100.00
rom_ctrl_kmac_err_chk 13.230s 3046.040us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.460s 1440.134us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.460s 1440.134us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 75.460s 1440.134us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.090s 3193.564us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 486.360s 10430.465us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 169.500s 2661.864us 1 1 100.00

Error Messages

   Test seed line log context