Simulation Results: rstmgr

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.48 %
  • code
  • 99.21 %
  • assert
  • 97.44 %
  • func
  • 95.78 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.30 %
  • toggle
  • 99.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.040s 56.788us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.310s 91.692us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.200s 36.596us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.310s 92.775us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.190s 45.339us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.890s 97.804us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.200s 36.596us 1 1 100.00
rstmgr_csr_aliasing 1.190s 45.339us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 2.300s 224.724us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.120s 40.717us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.240s 116.258us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.580s 577.806us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.580s 577.806us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.580s 577.806us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.580s 577.806us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 8.460s 913.872us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.910s 36.432us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.330s 67.593us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.330s 67.593us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.310s 91.692us 1 1 100.00
rstmgr_csr_rw 1.200s 36.596us 1 1 100.00
rstmgr_csr_aliasing 1.190s 45.339us 1 1 100.00
rstmgr_same_csr_outstanding 0.980s 37.789us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.310s 91.692us 1 1 100.00
rstmgr_csr_rw 1.200s 36.596us 1 1 100.00
rstmgr_csr_aliasing 1.190s 45.339us 1 1 100.00
rstmgr_same_csr_outstanding 0.980s 37.789us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 31.300s 6743.346us 1 1 100.00
rstmgr_tl_intg_err 4.220s 620.335us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 31.300s 6743.346us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 31.300s 6743.346us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 4.220s 620.335us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.070s 57.132us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.830s 422.653us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.090s 291.232us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 31.300s 6743.346us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.200s 36.596us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.200s 36.596us 1 1 100.00

Error Messages

   Test seed line log context