Simulation Results: rv_dm

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.38 %
  • code
  • 72.75 %
  • assert
  • 96.16 %
  • func
  • 57.24 %
  • line
  • 89.85 %
  • branch
  • 73.72 %
  • cond
  • 73.12 %
  • toggle
  • 70.83 %
  • FSM
  • 56.25 %
Validation stages
V1
93.55%
V2
64.29%
V2S
83.33%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 2.060s 2872.556us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 0.750s 461.022us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 0.740s 146.589us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 6.640s 5237.814us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 1.020s 449.487us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 7.560s 13702.711us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 3.040s 1764.468us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 60.870s 67426.190us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 108.520s 55340.894us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 0.990s 337.345us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 0.960s 410.467us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 0.800s 120.622us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 0.840s 238.797us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 0.850s 144.332us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 1.290s 417.560us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 0.900s 133.445us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 2.130s 1355.119us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 0.990s 337.345us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 0.800s 193.164us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 2.270s 990.043us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 0.800s 120.622us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 0.760s 193.288us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 1.790s 130.378us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 1.410s 289.381us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 18.130s 2847.347us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 20.450s 11921.784us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
rv_dm_csr_mem_rw_with_rand_reset 1.510s 143.774us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 20.450s 11921.784us 1 1 100.00
rv_dm_csr_rw 1.410s 289.381us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.660s 44.222us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.730s 86.918us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 2.060s 2872.556us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 1.070s 484.608us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 0.690s 112.498us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 0.960s 270.283us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 0.910s 592.262us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 307.220s 300000.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 78.460s 300000.000us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 155.550s 300000.000us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 158.730s 300000.000us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 0.670s 231.251us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 8.210s 4845.642us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 1.210s 283.155us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 0.610s 33.307us 0 1 0.00
tap_ctrl_transitions 1 2 50.00
rv_dm_tap_fsm_rand_reset 0.690s 31.783us 0 1 0.00
rv_dm_tap_fsm 12.790s 9889.876us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 0.790s 199.573us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 0.820s 379.245us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.620s 64.911us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
rv_dm_tl_errors 0.680s 95.065us 0 1 0.00
tl_d_illegal_access 0 1 0.00
rv_dm_tl_errors 0.680s 95.065us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 20.450s 11921.784us 1 1 100.00
rv_dm_csr_hw_reset 1.790s 130.378us 1 1 100.00
rv_dm_csr_rw 1.410s 289.381us 1 1 100.00
rv_dm_same_csr_outstanding 5.950s 1844.640us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 20.450s 11921.784us 1 1 100.00
rv_dm_csr_hw_reset 1.790s 130.378us 1 1 100.00
rv_dm_csr_rw 1.410s 289.381us 1 1 100.00
rv_dm_same_csr_outstanding 5.950s 1844.640us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_tl_intg_err 7.750s 1540.995us 1 1 100.00
rv_dm_sec_cm 1.380s 504.122us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 7.750s 1540.995us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 8.210s 4845.642us 1 1 100.00
rv_dm_debug_disabled 0.880s 111.375us 0 1 0.00
sec_cm_lc_dft_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 8.210s 4845.642us 1 1 100.00
rv_dm_debug_disabled 0.880s 111.375us 0 1 0.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 2.060s 2872.556us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 0.960s 480.928us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.830s 105.065us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.830s 105.065us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 0.960s 480.928us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 0.710s 27.387us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 182.760s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5720) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
rv_dm_tap_fsm_rand_reset 37206350238827357015795951715218823883334532942656272348599377269181955385001 76
UVM_ERROR @ 31783006 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5720) { a_addr: 'h1a967370 a_data: 'hecce9732 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h79 a_opcode: 'h4 a_user: 'h1baf5 d_param: 'h0 d_source: 'h79 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 31783006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6618) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
rv_dm_tl_errors 9840146562345759429858298316426653366461809418238442059833354522730195917696 75
UVM_ERROR @ 95064506 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6618) { a_addr: 'he5b1e764 a_data: 'h54a43191 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h4 a_user: 'h181a6 d_param: 'h0 d_source: 'h4 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 95064506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@20344) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
rv_dm_csr_mem_rw_with_rand_reset 2429603099824124958197201016802635540373327417471479663304927412484505294303 82
UVM_ERROR @ 143773942 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@20344) { a_addr: 'he32975e4 a_data: 'hcc36f69f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1c a_opcode: 'h4 a_user: 'h1b479 d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 143773942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
rv_dm_sba_tl_access 61611758856577877907253987407388246466484160104040730983292989552760119544131 83
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 42747487834561565537849975566594298434589835243277886178641418903058763656996 83
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 65328985011687531751725170591533029504476484621043070715866591527825418376676 83
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 51154287428865598275437309543779958449531580517872987373507375362668873475572 83
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_scanmode 29211841192245312498295186247491252870660484550106799585431217303350944403748 74
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*])
rv_dm_mem_tl_access_resuming 104069999770724483083002536679306475541979979515709918618795368018024736916832 74
UVM_ERROR @ 238797365 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 238797365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [*] vs * [*])
rv_dm_hart_unavail 42046433199665793114336532947728698125803807569370733451799511723134757349582 74
UVM_ERROR @ 33307332 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 33307332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])
rv_dm_jtag_dmi_debug_disabled 34192300851856104428786383775655627483413021195791317934671396422766679029778 74
UVM_ERROR @ 231251451 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1844738184 [0x6df47888] vs 0 [0x0])
UVM_INFO @ 231251451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 105493622117203736919269674293100208209480453567570979255914895131342552081408 76
UVM_ERROR @ 379244985 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3674699051 [0xdb07752b] vs 0 [0x0])
UVM_INFO @ 379244985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:446) [scoreboard] Check failed (item.d_error)
rv_dm_debug_disabled 51235538355058614425779900756930911119703363720774661334947057225800782395170 77
UVM_ERROR @ 111374558 ps: (rv_dm_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed (item.d_error)
UVM_INFO @ 111374558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5770) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
rv_dm_stress_all_with_rand_reset 69650059499448094504169467304932431068545205052905724099807198506663344697695 76
UVM_ERROR @ 27386940 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5770) { a_addr: 'h4c673648 a_data: 'ha1def4e1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h4 a_user: 'h19e5d d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 27386940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---