Simulation Results: rv_timer

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.13 %
  • code
  • 99.92 %
  • assert
  • 96.82 %
  • func
  • 82.65 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 99.69 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.550s 203.093us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.610s 26.387us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.630s 21.118us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.400s 1201.692us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.690s 68.277us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.850s 72.522us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.630s 21.118us 1 1 100.00
rv_timer_csr_aliasing 0.690s 68.277us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.080s 439.773us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.880s 1299.400us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 1.300s 1205.928us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 1.300s 1205.928us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.510s 22614.035us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.540s 162.539us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.630s 60.748us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.230s 565.218us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.230s 565.218us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 26.387us 1 1 100.00
rv_timer_csr_rw 0.630s 21.118us 1 1 100.00
rv_timer_csr_aliasing 0.690s 68.277us 1 1 100.00
rv_timer_same_csr_outstanding 0.760s 158.092us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 26.387us 1 1 100.00
rv_timer_csr_rw 0.630s 21.118us 1 1 100.00
rv_timer_csr_aliasing 0.690s 68.277us 1 1 100.00
rv_timer_same_csr_outstanding 0.760s 158.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.910s 60.206us 1 1 100.00
rv_timer_tl_intg_err 1.350s 121.147us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.350s 121.147us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.850s 658.994us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.590s 151.980us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 4.510s 867.764us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 46582402663318988578283934069635851092647396573429180463838241088213958811353 72
UVM_FATAL @ 658993735 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe0f4b104) == 0x1
UVM_INFO @ 658993735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 98685048440642423283861164102986317551036997704166319721705960403078814702861 72
UVM_FATAL @ 439772697 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x33494f04) == 0x1
UVM_INFO @ 439772697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 92773566749129764853418868203911235826830790605926591766516211729128259456928 72
UVM_ERROR @ 151980147 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 151980147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
rv_timer_stress_all_with_rand_reset 42593454616756431038573330538837043523465737581815352146165838766669679681425 93
UVM_ERROR @ 867763641 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 867763641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---