Simulation Results: spi_host

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.52 %
  • code
  • 94.86 %
  • assert
  • 95.21 %
  • func
  • 87.50 %
  • block
  • 96.64 %
  • line
  • 98.47 %
  • branch
  • 92.95 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 7.000s 328.150us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 18.921us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 64.251us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 319.191us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 144.473us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 43.191us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 64.251us 1 1 100.00
spi_host_csr_aliasing 2.000s 144.473us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 104.290us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 42.137us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 35.768us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 58.949us 1 1 100.00
spi_host_error_cmd 2.000s 19.963us 1 1 100.00
spi_host_event 17.000s 3519.988us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 129.163us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 129.163us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 129.163us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 6.000s 236.250us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 132.345us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 129.163us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 129.163us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 7.000s 328.150us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 7.000s 328.150us 1 1 100.00
stress_all 0 1 0.00
spi_host_stress_all 705.000s 1000000.000us 0 1 0.00
spien 1 1 100.00
spi_host_spien 6.000s 813.910us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 51.000s 10619.636us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 235.371us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 58.949us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 36.683us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 18.836us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 1.000s 112.401us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 1.000s 112.401us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 18.921us 1 1 100.00
spi_host_csr_rw 1.000s 64.251us 1 1 100.00
spi_host_csr_aliasing 2.000s 144.473us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 22.544us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 18.921us 1 1 100.00
spi_host_csr_rw 1.000s 64.251us 1 1 100.00
spi_host_csr_aliasing 2.000s 144.473us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 22.544us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 61.689us 1 1 100.00
spi_host_sec_cm 2.000s 129.037us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 61.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 38.000s 910.154us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_stress_all 108313565268934547457228676885339558843860601932356624903431467648918509207527 242
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---