Simulation Results: sram_ctrl

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.81 %
  • code
  • 93.76 %
  • assert
  • 95.69 %
  • func
  • 94.99 %
  • line
  • 98.57 %
  • branch
  • 96.53 %
  • cond
  • 92.53 %
  • toggle
  • 90.71 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.470s 1780.302us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.950s 17.971us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.980s 53.061us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.470s 461.163us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.930s 34.370us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.550s 1364.586us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.980s 53.061us 1 1 100.00
sram_ctrl_csr_aliasing 0.930s 34.370us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 244.060s 149578.263us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 45.550s 967.382us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 353.560s 11533.833us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 107.050s 2119.484us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 720.390s 30741.100us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 381.360s 10376.049us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 32.010s 9497.033us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 116.960s 9328.356us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 8.470s 3556.323us 1 1 100.00
sram_ctrl_partial_access_b2b 326.520s 36734.968us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 18.790s 733.684us 1 1 100.00
sram_ctrl_throughput_w_partial_write 15.140s 2846.359us 1 1 100.00
sram_ctrl_throughput_w_readback 5.840s 1400.805us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 741.660s 72366.806us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.060s 373.114us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1820.660s 444455.985us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.970s 122.606us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.190s 590.914us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.190s 590.914us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.950s 17.971us 1 1 100.00
sram_ctrl_csr_rw 0.980s 53.061us 1 1 100.00
sram_ctrl_csr_aliasing 0.930s 34.370us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.960s 23.244us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.950s 17.971us 1 1 100.00
sram_ctrl_csr_rw 0.980s 53.061us 1 1 100.00
sram_ctrl_csr_aliasing 0.930s 34.370us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.960s 23.244us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.860s 7408.112us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.720s 4.736us 0 1 0.00
sram_ctrl_tl_intg_err 1.740s 265.120us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.720s 4.736us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.740s 265.120us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 741.660s 72366.806us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 741.660s 72366.806us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.980s 53.061us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 116.960s 9328.356us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 116.960s 9328.356us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 116.960s 9328.356us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 32.010s 9497.033us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.220s 2775.220us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.860s 7408.112us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.290s 698.604us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.470s 1780.302us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.470s 1780.302us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 116.960s 9328.356us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.720s 4.736us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 32.010s 9497.033us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.720s 4.736us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.720s 4.736us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.470s 1780.302us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.720s 4.736us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 146.970s 21145.436us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 14362521086482620324365468877236539329011865675297267624985943870141201984226 97
UVM_ERROR @ 4735659 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 4735659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---