Simulation Results: sram_ctrl

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.19 %
  • code
  • 90.33 %
  • assert
  • 95.37 %
  • func
  • 93.88 %
  • line
  • 97.68 %
  • branch
  • 95.71 %
  • cond
  • 91.43 %
  • toggle
  • 90.62 %
  • FSM
  • 76.19 %
Validation stages
V1
90.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 8.530s 710.780us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.810s 18.362us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.740s 35.627us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.370s 198.660us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.840s 44.056us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.610s 98.501us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.740s 35.627us 1 1 100.00
sram_ctrl_csr_aliasing 0.840s 44.056us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 9.220s 2301.520us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.880s 215.406us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 441.360s 49452.509us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 190.200s 10304.606us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 33.010s 2823.913us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 706.180s 9070.065us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.610s 736.118us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 445.220s 6000.198us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 13.010s 771.203us 1 1 100.00
sram_ctrl_partial_access_b2b 320.220s 20604.244us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 50.640s 132.246us 1 1 100.00
sram_ctrl_throughput_w_partial_write 7.240s 244.190us 1 1 100.00
sram_ctrl_throughput_w_readback 44.390s 323.140us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 351.710s 5872.783us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.800s 49.203us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 963.640s 3991.084us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.920s 24.881us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.310s 166.348us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.310s 166.348us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.810s 18.362us 1 1 100.00
sram_ctrl_csr_rw 0.740s 35.627us 1 1 100.00
sram_ctrl_csr_aliasing 0.840s 44.056us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.770s 78.746us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.810s 18.362us 1 1 100.00
sram_ctrl_csr_rw 0.740s 35.627us 1 1 100.00
sram_ctrl_csr_aliasing 0.840s 44.056us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.770s 78.746us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.670s 458.622us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.830s 4.371us 0 1 0.00
sram_ctrl_tl_intg_err 1.300s 151.272us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.830s 4.371us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.300s 151.272us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 351.710s 5872.783us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 351.710s 5872.783us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.740s 35.627us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 445.220s 6000.198us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 445.220s 6000.198us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 445.220s 6000.198us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.610s 736.118us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 0.980s 67.195us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.670s 458.622us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.080s 34.286us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 8.530s 710.780us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 8.530s 710.780us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 445.220s 6000.198us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.830s 4.371us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.610s 736.118us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.830s 4.371us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.830s 4.371us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 8.530s 710.780us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.830s 4.371us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 45.300s 2258.623us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 91598208276603663975227818510583985121667658691385909265377293274686345690916 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 4371498 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 4371498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 85880378752147835282769673908914243295641006711177354677965466932436981925442 95
UVM_ERROR @ 98500619 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
UVM_INFO @ 98500619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---