Simulation Results: uart

 
10/12/2025 16:08:41 sha: 141563d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.40 %
  • code
  • 96.68 %
  • assert
  • 97.12 %
  • func
  • 47.39 %
  • line
  • 99.38 %
  • branch
  • 97.90 %
  • cond
  • 97.90 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
91.18%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.640s 531.414us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.570s 64.784us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.610s 54.736us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.910s 340.505us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.720s 156.378us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.660s 19.898us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.610s 54.736us 1 1 100.00
uart_csr_aliasing 0.720s 156.378us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 29.750s 159903.544us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.640s 531.414us 1 1 100.00
uart_tx_rx 29.750s 159903.544us 1 1 100.00
parity_error 2 2 100.00
uart_intr 7.040s 27023.655us 1 1 100.00
uart_rx_parity_err 24.160s 155391.697us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 29.750s 159903.544us 1 1 100.00
uart_intr 7.040s 27023.655us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 23.640s 20774.554us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 18.370s 59345.438us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 143.510s 143122.461us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 7.040s 27023.655us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 7.040s 27023.655us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 7.040s 27023.655us 1 1 100.00
perf 0 1 0.00
uart_perf 27.520s 11988.243us 0 1 0.00
sys_loopback 1 1 100.00
uart_loopback 9.160s 8227.950us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 9.160s 8227.950us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 3.260s 2460.830us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 8.020s 39591.116us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.420s 1817.641us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 23.550s 6787.727us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 214.430s 90754.542us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 60.300s 55762.980us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.610s 35.272us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.680s 25.019us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.610s 378.785us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.610s 378.785us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.570s 64.784us 1 1 100.00
uart_csr_rw 0.610s 54.736us 1 1 100.00
uart_csr_aliasing 0.720s 156.378us 1 1 100.00
uart_same_csr_outstanding 0.720s 114.894us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.570s 64.784us 1 1 100.00
uart_csr_rw 0.610s 54.736us 1 1 100.00
uart_csr_aliasing 0.720s 156.378us 1 1 100.00
uart_same_csr_outstanding 0.720s 114.894us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.830s 118.169us 1 1 100.00
uart_tl_intg_err 0.850s 229.635us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.850s 229.635us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 37.660s 9465.764us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_noise_filter 10190234845077159214144839003950759775847540602889911798337707374205487537763 71
UVM_ERROR @ 39915530 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 39915530 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 289300549 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 289300549 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 289300549 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty
uart_perf 69923182083786006596608983124437477626523007080758861016941328859609474448941 74
UVM_ERROR @ 8929388945 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
UVM_INFO @ 10089380016 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/5
UVM_INFO @ 11521957781 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 5/5
UVM_INFO @ 11988243034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_stress_all 64650770483460836328140597084586918864351915713698393223566801345773410388299 105
UVM_ERROR @ 55350364653 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 55350376558 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 55350388463 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (192 [0xc0] vs 251 [0xfb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 55350400368 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 55350412273 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (192 [0xc0] vs 191 [0xbf]) reg name: uart_reg_block.rdata