| V1 |
|
100.00% |
| V2 |
|
97.14% |
| V2S |
|
98.48% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| aes_wake_up | 2.000s | 80.433us | 1 | 1 | 100.00 | |
| smoke | 1 | 1 | 100.00 | |||
| aes_smoke | 3.000s | 106.443us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 57.645us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| aes_csr_rw | 2.000s | 81.096us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aes_csr_bit_bash | 6.000s | 545.845us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aes_csr_aliasing | 2.000s | 242.365us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| aes_csr_mem_rw_with_rand_reset | 1.000s | 108.656us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| aes_csr_rw | 2.000s | 81.096us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 2.000s | 242.365us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| algorithm | 3 | 3 | 100.00 | |||
| aes_smoke | 3.000s | 106.443us | 1 | 1 | 100.00 | |
| aes_config_error | 3.000s | 140.550us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 188.864us | 1 | 1 | 100.00 | |
| key_length | 3 | 3 | 100.00 | |||
| aes_smoke | 3.000s | 106.443us | 1 | 1 | 100.00 | |
| aes_config_error | 3.000s | 140.550us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 188.864us | 1 | 1 | 100.00 | |
| back2back | 2 | 2 | 100.00 | |||
| aes_stress | 3.000s | 188.864us | 1 | 1 | 100.00 | |
| aes_b2b | 6.000s | 301.869us | 1 | 1 | 100.00 | |
| backpressure | 1 | 1 | 100.00 | |||
| aes_stress | 3.000s | 188.864us | 1 | 1 | 100.00 | |
| multi_message | 4 | 4 | 100.00 | |||
| aes_smoke | 3.000s | 106.443us | 1 | 1 | 100.00 | |
| aes_config_error | 3.000s | 140.550us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 188.864us | 1 | 1 | 100.00 | |
| aes_alert_reset | 4.000s | 439.464us | 1 | 1 | 100.00 | |
| failure_test | 3 | 3 | 100.00 | |||
| aes_man_cfg_err | 2.000s | 91.026us | 1 | 1 | 100.00 | |
| aes_config_error | 3.000s | 140.550us | 1 | 1 | 100.00 | |
| aes_alert_reset | 4.000s | 439.464us | 1 | 1 | 100.00 | |
| trigger_clear_test | 1 | 1 | 100.00 | |||
| aes_clear | 4.000s | 169.910us | 1 | 1 | 100.00 | |
| nist_test_vectors | 1 | 1 | 100.00 | |||
| aes_nist_vectors | 8.000s | 206.889us | 1 | 1 | 100.00 | |
| reset_recovery | 1 | 1 | 100.00 | |||
| aes_alert_reset | 4.000s | 439.464us | 1 | 1 | 100.00 | |
| stress | 1 | 1 | 100.00 | |||
| aes_stress | 3.000s | 188.864us | 1 | 1 | 100.00 | |
| sideload | 2 | 2 | 100.00 | |||
| aes_stress | 3.000s | 188.864us | 1 | 1 | 100.00 | |
| aes_sideload | 5.000s | 109.959us | 1 | 1 | 100.00 | |
| deinitialization | 1 | 1 | 100.00 | |||
| aes_deinit | 3.000s | 239.625us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| aes_stress_all | 33.000s | 4501.944us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| aes_alert_test | 2.000s | 78.781us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| aes_tl_errors | 4.000s | 231.527us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| aes_tl_errors | 4.000s | 231.527us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 57.645us | 1 | 1 | 100.00 | |
| aes_csr_rw | 2.000s | 81.096us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 2.000s | 242.365us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 2.000s | 116.583us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 57.645us | 1 | 1 | 100.00 | |
| aes_csr_rw | 2.000s | 81.096us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 2.000s | 242.365us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 2.000s | 116.583us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reseeding | 1 | 1 | 100.00 | |||
| aes_reseed | 4.000s | 175.892us | 1 | 1 | 100.00 | |
| fault_inject | 3 | 3 | 100.00 | |||
| aes_fi | 4.000s | 94.636us | 1 | 1 | 100.00 | |
| aes_control_fi | 3.000s | 77.679us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 48.384us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 202.838us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 202.838us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 202.838us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 202.838us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors_with_csr_rw | 3.000s | 196.347us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| aes_tl_intg_err | 3.000s | 203.786us | 1 | 1 | 100.00 | |
| aes_sec_cm | 14.000s | 2377.183us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| aes_tl_intg_err | 3.000s | 203.786us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| aes_alert_reset | 4.000s | 439.464us | 1 | 1 | 100.00 | |
| sec_cm_main_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 202.838us | 1 | 1 | 100.00 | |
| sec_cm_gcm_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 202.838us | 1 | 1 | 100.00 | |
| sec_cm_main_config_sparse | 3 | 4 | 75.00 | |||
| aes_smoke | 3.000s | 106.443us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 188.864us | 1 | 1 | 100.00 | |
| aes_alert_reset | 4.000s | 439.464us | 1 | 1 | 100.00 | |
| aes_core_fi | 33.000s | 10006.561us | 0 | 1 | 0.00 | |
| sec_cm_gcm_config_sparse | 2 | 2 | 100.00 | |||
| aes_config_error | 3.000s | 140.550us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 188.864us | 1 | 1 | 100.00 | |
| sec_cm_aux_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 202.838us | 1 | 1 | 100.00 | |
| sec_cm_aux_config_regwen | 2 | 2 | 100.00 | |||
| aes_readability | 2.000s | 84.649us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 188.864us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 2 | 2 | 100.00 | |||
| aes_stress | 3.000s | 188.864us | 1 | 1 | 100.00 | |
| aes_sideload | 5.000s | 109.959us | 1 | 1 | 100.00 | |
| sec_cm_key_sw_unreadable | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 84.649us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_unreadable | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 84.649us | 1 | 1 | 100.00 | |
| sec_cm_key_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 84.649us | 1 | 1 | 100.00 | |
| sec_cm_iv_config_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 84.649us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 84.649us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_key_sca | 1 | 1 | 100.00 | |||
| aes_stress | 3.000s | 188.864us | 1 | 1 | 100.00 | |
| sec_cm_key_masking | 1 | 1 | 100.00 | |||
| aes_stress | 3.000s | 188.864us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_sparse | 1 | 1 | 100.00 | |||
| aes_fi | 4.000s | 94.636us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_redun | 4 | 4 | 100.00 | |||
| aes_fi | 4.000s | 94.636us | 1 | 1 | 100.00 | |
| aes_control_fi | 3.000s | 77.679us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 48.384us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 90.591us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_sparse | 1 | 1 | 100.00 | |||
| aes_fi | 4.000s | 94.636us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_redun | 3 | 3 | 100.00 | |||
| aes_fi | 4.000s | 94.636us | 1 | 1 | 100.00 | |
| aes_control_fi | 3.000s | 77.679us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 48.384us | 1 | 1 | 100.00 | |
| sec_cm_cipher_ctr_redun | 1 | 1 | 100.00 | |||
| aes_cipher_fi | 2.000s | 48.384us | 1 | 1 | 100.00 | |
| sec_cm_ctr_fsm_sparse | 1 | 1 | 100.00 | |||
| aes_fi | 4.000s | 94.636us | 1 | 1 | 100.00 | |
| sec_cm_ctr_fsm_redun | 3 | 3 | 100.00 | |||
| aes_fi | 4.000s | 94.636us | 1 | 1 | 100.00 | |
| aes_control_fi | 3.000s | 77.679us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 90.591us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_sparse | 4 | 4 | 100.00 | |||
| aes_fi | 4.000s | 94.636us | 1 | 1 | 100.00 | |
| aes_control_fi | 3.000s | 77.679us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 48.384us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 90.591us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_global_esc | 1 | 1 | 100.00 | |||
| aes_alert_reset | 4.000s | 439.464us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_local_esc | 4 | 4 | 100.00 | |||
| aes_fi | 4.000s | 94.636us | 1 | 1 | 100.00 | |
| aes_control_fi | 3.000s | 77.679us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 48.384us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 90.591us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_local_esc | 4 | 4 | 100.00 | |||
| aes_fi | 4.000s | 94.636us | 1 | 1 | 100.00 | |
| aes_control_fi | 3.000s | 77.679us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 48.384us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 90.591us | 1 | 1 | 100.00 | |
| sec_cm_ctr_fsm_local_esc | 3 | 3 | 100.00 | |||
| aes_fi | 4.000s | 94.636us | 1 | 1 | 100.00 | |
| aes_control_fi | 3.000s | 77.679us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 2.000s | 90.591us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_local_esc | 3 | 3 | 100.00 | |||
| aes_fi | 4.000s | 94.636us | 1 | 1 | 100.00 | |
| aes_control_fi | 3.000s | 77.679us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 48.384us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| aes_stress_all_with_rand_reset | 9.000s | 334.504us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! | ||||
| aes_core_fi | 64190068103875606589584910383000235676144095061049041499785251579787317784516 | 136 |
UVM_FATAL @ 10006560890 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10006560890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1122): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) | ||||
| aes_stress_all | 84231561938456826862507059168210763769778971577716141477105824699203742927114 | 208260 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,1122): (time 4501944165 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 4501860832 PS)
UVM_ERROR @ 4501944165 ps: (aes_core.sv:1122) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
UVM_INFO @ 4501944165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) | ||||
| aes_stress_all_with_rand_reset | 88407729784561552033842255530561622522721238365617798949897900397293945732251 | 360 |
UVM_FATAL @ 334504137 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 334504137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|