clkmgr Simulation Results

Simulation Results: clkmgr

11/12/2025 16:10:21 sha: 9c781e9 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
76.39 %

code
68.78 %

assert
89.67 %

func
70.73 %

line
81.68 %

branch
86.59 %

cond
78.53 %

toggle
97.08 %

FSM
0.00 %

Validation stages

V1		37.50%
V2		57.89%
V2S		35.29%
V3		0.00%

3/8 passed

37.50 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	clkmgr_smoke	1.300s	83.498us	1	1	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	0.710s	19.761us	1	1	100.00
csr_rw				0	1	0.00
	clkmgr_csr_rw	0.580s	3.640us	0	1	0.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	1.930s	86.192us	0	1	0.00
csr_aliasing				0	1	0.00
	clkmgr_csr_aliasing	0.860s	32.328us	0	1	0.00
csr_mem_rw_with_rand_reset				1	1	100.00
	clkmgr_csr_mem_rw_with_rand_reset	1.100s	65.053us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				0	2	0.00
	clkmgr_csr_rw	0.580s	3.640us	0	1	0.00
	clkmgr_csr_aliasing	0.860s	32.328us	0	1	0.00

11/19 passed

57.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				1	1	100.00
	clkmgr_peri	0.790s	24.236us	1	1	100.00
trans_enables				1	1	100.00
	clkmgr_trans	0.850s	27.468us	1	1	100.00
clk_status				1	1	100.00
	clkmgr_clk_status	0.810s	18.653us	1	1	100.00
jitter				1	1	100.00
	clkmgr_smoke	1.300s	83.498us	1	1	100.00
frequency				0	1	0.00
	clkmgr_frequency	0.780s	6.341us	0	1	0.00
frequency_timeout				0	1	0.00
	clkmgr_frequency_timeout	0.670s	3.080us	0	1	0.00
frequency_overflow				0	1	0.00
	clkmgr_frequency	0.780s	6.341us	0	1	0.00
stress_all				0	1	0.00
	clkmgr_stress_all	0.640s	9.388us	0	1	0.00
alert_test				1	1	100.00
	clkmgr_alert_test	0.860s	24.635us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	clkmgr_tl_errors	3.400s	257.396us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	clkmgr_tl_errors	3.400s	257.396us	1	1	100.00
tl_d_outstanding_access				2	4	50.00
	clkmgr_csr_hw_reset	0.710s	19.761us	1	1	100.00
	clkmgr_csr_rw	0.580s	3.640us	0	1	0.00
	clkmgr_csr_aliasing	0.860s	32.328us	0	1	0.00
	clkmgr_same_csr_outstanding	0.940s	38.326us	1	1	100.00
tl_d_partial_access				2	4	50.00
	clkmgr_csr_hw_reset	0.710s	19.761us	1	1	100.00
	clkmgr_csr_rw	0.580s	3.640us	0	1	0.00
	clkmgr_csr_aliasing	0.860s	32.328us	0	1	0.00
	clkmgr_same_csr_outstanding	0.940s	38.326us	1	1	100.00

V2S

6/17 passed

35.29 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				0	2	0.00
	clkmgr_sec_cm	0.680s	7.002us	0	1	0.00
	clkmgr_tl_intg_err	0.680s	10.131us	0	1	0.00
shadow_reg_update_error				1	1	100.00
	clkmgr_shadow_reg_errors	2.020s	156.931us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	clkmgr_shadow_reg_errors	2.020s	156.931us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	clkmgr_shadow_reg_errors	2.020s	156.931us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	clkmgr_shadow_reg_errors	2.020s	156.931us	1	1	100.00
shadow_reg_update_error_with_csr_rw				0	1	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	0.690s	6.453us	0	1	0.00
sec_cm_bus_integrity				0	1	0.00
	clkmgr_tl_intg_err	0.680s	10.131us	0	1	0.00
sec_cm_meas_clk_bkgn_chk				0	1	0.00
	clkmgr_frequency	0.780s	6.341us	0	1	0.00
sec_cm_timeout_clk_bkgn_chk				0	1	0.00
	clkmgr_frequency_timeout	0.670s	3.080us	0	1	0.00
sec_cm_meas_config_shadow				1	1	100.00
	clkmgr_shadow_reg_errors	2.020s	156.931us	1	1	100.00
sec_cm_idle_intersig_mubi				1	1	100.00
	clkmgr_idle_intersig_mubi	1.570s	120.907us	1	1	100.00
sec_cm_jitter_config_mubi				0	1	0.00
	clkmgr_csr_rw	0.580s	3.640us	0	1	0.00
sec_cm_idle_ctr_redun				0	1	0.00
	clkmgr_sec_cm	0.680s	7.002us	0	1	0.00
sec_cm_meas_config_regwen				0	1	0.00
	clkmgr_csr_rw	0.580s	3.640us	0	1	0.00
sec_cm_clk_ctrl_config_regwen				0	1	0.00
	clkmgr_csr_rw	0.580s	3.640us	0	1	0.00
prim_count_check				0	1	0.00
	clkmgr_sec_cm	0.680s	7.002us	0	1	0.00

0/2 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
regwen				1
	clkmgr_regwen	0.570s	2.585us	1
stress_all_with_rand_reset				1
	clkmgr_stress_all_with_rand_reset	4.560s	406.189us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b
	clkmgr_frequency	11532029485706222215201718011907687613190137281467242632702178447134400382111	73	UVM_ERROR @ 6341090 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00 UVM_INFO @ 6341090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	83278472860621265667136010493590669857308123266798273138123457607844520425956	72	UVM_ERROR @ 9388203 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00 UVM_INFO @ 9388203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b
	clkmgr_frequency_timeout	57817986215678925917654212253856363564224407050287095313632181456817760377895	75	UVM_ERROR @ 3079664 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00 UVM_INFO @ 3079664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	20750436838168969491625763908805643344193861547867398699124417342591593924047	114	UVM_ERROR @ 406189061 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00 UVM_INFO @ 406189061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en
	clkmgr_regwen	73111284321082149424398765929156843064304965954871736929779261961977682872739	71	UVM_ERROR @ 2585009 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en UVM_INFO @ 2585009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
	clkmgr_sec_cm	6339554684617941305478439536039414748731045473139976777038751898376278264863	79	UVM_ERROR @ 7001697 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 7001697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:
	clkmgr_shadow_reg_errors_with_csr_rw	57862850393012552037100501015073228110781924377842214991644570929938225715155	72	UVM_ERROR @ 6453452 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 UVM_INFO @ 6453452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	100428868503258414821281314903264691594802203199685485131707572402449242829412	75	UVM_ERROR @ 10130790 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 UVM_INFO @ 10130790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_aliasing	41126688157778950323176227907595967174112585474202372488114477744384632681054	72	UVM_ERROR @ 32328416 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 UVM_INFO @ 32328416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:
	clkmgr_csr_rw	67871673441640877247654377839089498437592290362878184475210703838228098170361	72	UVM_ERROR @ 3640159 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 UVM_INFO @ 3640159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:
	clkmgr_csr_bit_bash	109945309386964264188131409206800396038805354587333269529896876803818818256239	72	UVM_ERROR @ 86192195 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0 UVM_INFO @ 86192195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---