Simulation Results: dma

 
11/12/2025 16:10:21 sha: 9c781e9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.33 %
  • code
  • 91.85 %
  • assert
  • 95.66 %
  • func
  • 62.47 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 6.000s 225.676us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 354.486us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 616.514us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 80.345us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 87.789us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 7.000s 8270.779us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 233.947us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 104.245us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 87.789us 1 1 100.00
dma_csr_aliasing 3.000s 233.947us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 52.000s 16445.299us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 159.000s 60444.657us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 152.000s 12453.571us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 152.000s 12453.571us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 159.000s 60444.657us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 970.000s 376501.969us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 152.000s 12453.571us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 14.000s 1114.025us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 55.000s 5130.078us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 14.260us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 15.918us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 4.000s 248.409us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 4.000s 248.409us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 80.345us 1 1 100.00
dma_csr_rw 2.000s 87.789us 1 1 100.00
dma_csr_aliasing 3.000s 233.947us 1 1 100.00
dma_same_csr_outstanding 2.000s 53.398us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 80.345us 1 1 100.00
dma_csr_rw 2.000s 87.789us 1 1 100.00
dma_csr_aliasing 3.000s 233.947us 1 1 100.00
dma_same_csr_outstanding 2.000s 53.398us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 10.000s 54.632us 1 1 100.00
dma_generic_stress 970.000s 376501.969us 1 1 100.00
dma_handshake_stress 152.000s 12453.571us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 8.000s 1368.992us 1 1 100.00
tl_intg_err 2 2 100.00
dma_sec_cm 1.000s 34.760us 1 1 100.00
dma_tl_intg_err 4.000s 791.614us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 143.000s 37846.611us 1 1 100.00
dma_longer_transfer 5.000s 199.772us 1 1 100.00
dma_stress_all_with_rand_reset 9.000s 9780.655us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 13072456045033237224947676036328301156957588367380187336466550548691482207136 100
UVM_ERROR @ 9780655459ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9780655459ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---