| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| edn_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| edn_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 0 | 1 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| default | None | None |
File "/nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py", line 88, in <module>
main()
~~~~^^
File "/nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py", line 32, in main
gapi = yaml.load(open(gapi_filepath), Loader=YamlLoader)
~~~~^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: '/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d/ral_input.yml'
ERROR: Could not find EDA API file "/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d"
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
|
|
| cover_reg_top | None | None |
File "/nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py", line 88, in <module>
main()
~~~~^^
File "/nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py", line 32, in main
gapi = yaml.load(open(gapi_filepath), Loader=YamlLoader)
~~~~^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: '/nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d/ral_input.yml'
ERROR: Could not find EDA API file "/nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d"
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| edn_smoke | 94432929359531228238646665878818794078882099976701609932292441660103393565473 | None | ||
| edn_regwen | 88048126311118129892754006199425474171830591669355667139712502590161964297847 | None | ||
| edn_genbits | 54339951132632330335586485107547843106108178428269123930287228318667826816713 | None | ||
| edn_stress_all | 37096588295649074561858790767547828906074876950983675798248445027988629354625 | None | ||
| edn_stress_all_with_rand_reset | 109131485699601083917206126484180775544096527230543798207299299605103194921744 | None | ||
| edn_intr | 86632150967963020688631396076537787623531175523844211284775772096281595729377 | None | ||
| edn_alert | 43047912349266356240371034303808828112021585243444921937277725848415813151903 | None | ||
| edn_err | 100893322259264144555906961343834586586001957944695648456717855365136521063278 | None | ||
| edn_disable | 110252913804756405903829183073350643531602947932025675438865580435280282889371 | None | ||
| edn_disable_auto_req_mode | 82278087697329063413868795065286617340960752544381027435353067989940619694519 | None | ||
| edn_sec_cm | 99646906892953545309421989669053031691063830053247463509065559622744395296588 | None | ||
| edn_alert_test | 63196724116539961935169768019025621093174060278707515137966400643648699564947 | None | ||
| edn_tl_errors | 75333071504770852001458556675076662645538752006332719541781318753752664906222 | None | ||
| edn_tl_intg_err | 69881830305986273277543829581168497264464247009018777478513187030423148479528 | None | ||
| edn_intr_test | 74276528109719296303895527144663572826409263583123448412899113186894177879555 | None | ||
| edn_csr_hw_reset | 35351454251239012256139817279931718313311901689670029854950738476311770851821 | None | ||
| edn_csr_rw | 548396622154680929668372374129131184996155048769853857070765573834470289749 | None | ||
| edn_csr_bit_bash | 72809229126414599326554626987888405736172367005217040193467226931033651594251 | None | ||
| edn_csr_aliasing | 84183152303421266716241539230948606688769740302608686464741404153234885552452 | None | ||
| edn_same_csr_outstanding | 60328586351101107162413974682686022598815633328779582422003134861538105395034 | None | ||
| edn_csr_mem_rw_with_rand_reset | 42883953656798314449733322937910223012773584081330004079855463825489718896606 | None | ||
| edn | None | None | ||
| edn | None | None | ||