| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| edn_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| edn_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 0 | 1 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| default | None | None |
Traceback (most recent call last):
File "/nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py", line 88, in <module>
main()
~~~~^^
File "/nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py", line 32, in main
gapi = yaml.load(open(gapi_filepath), Loader=YamlLoader)
~~~~^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: '/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d/ral_input.yml'
ERROR: Could not find EDA API file "/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d"
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
|
|
| cover_reg_top | None | None |
File "/nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py", line 88, in <module>
main()
~~~~^^
File "/nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py", line 32, in main
gapi = yaml.load(open(gapi_filepath), Loader=YamlLoader)
~~~~^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: '/nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d/ral_input.yml'
ERROR: Could not find EDA API file "/nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d"
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| edn_smoke | 12950253732886133646157614341599984132904814123506430586940167205121046381513 | None | ||
| edn_regwen | 42626925070439947264766918695710506888715225138707274348676381950125937270817 | None | ||
| edn_genbits | 37936603667910875850173390322326407419184504314962309308357783538695423910144 | None | ||
| edn_stress_all | 9158739115863008927908647442408749646183786164487233318535879831703909871975 | None | ||
| edn_stress_all_with_rand_reset | 91862851284467592757606575327820953740847078839089548522693844998648213859327 | None | ||
| edn_intr | 18845181103073996862115255928520149163660504940692080021433326673197914201551 | None | ||
| edn_alert | 40779625636849070889503385700288396549454091431290691604295320693694922564232 | None | ||
| edn_err | 64770951688214904424714551197285211416380151020370992307779353913528128779334 | None | ||
| edn_disable | 19420972564412794898517201679548887359509213306767340012840100589628453115353 | None | ||
| edn_disable_auto_req_mode | 106339307685789207085033155906043929902087345350514021539407860556738160347063 | None | ||
| edn_sec_cm | 59337128908677078395995995097166331728583226472163525612604577193296428066188 | None | ||
| edn_alert_test | 6110812050806917601963505405079132663579432148601345358052430120314945937958 | None | ||
| edn_tl_errors | 21077003123866412529749932587370983952316394671495808231749247975971134188171 | None | ||
| edn_tl_intg_err | 89031515274834818343647184270897775532636241967287706336327127687828397170750 | None | ||
| edn_intr_test | 75022136325845437990271994088102460086905287276487819909064702343867231727311 | None | ||
| edn_csr_hw_reset | 70464518918903082863767296256212979385259534942410958391339543906356408564565 | None | ||
| edn_csr_rw | 37897413565185892659658256050408694667077682233333369492530073059486443722974 | None | ||
| edn_csr_bit_bash | 28407861447236540059086965410181647725188988578845795440077808566673870571384 | None | ||
| edn_csr_aliasing | 115472246815188550821718229606604669653039224319033796061790983701426519427611 | None | ||
| edn_same_csr_outstanding | 60392723414852635154588905833203411059236129762303393120871232935636240208841 | None | ||
| edn_csr_mem_rw_with_rand_reset | 67158825697835491466193503000138001628646325522880153190819918503789730515990 | None | ||
| edn | None | None | ||
| edn | None | None | ||