Simulation Results: hmac

 
11/12/2025 16:10:21 sha: 9c781e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.68 %
  • code
  • 97.35 %
  • assert
  • 97.14 %
  • func
  • 44.55 %
  • line
  • 99.68 %
  • branch
  • 99.34 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 9.600s 261.450us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.930s 85.640us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.060s 252.074us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.250s 460.182us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.410s 1039.225us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 12.590s 1009.826us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.060s 252.074us 1 1 100.00
hmac_csr_aliasing 4.410s 1039.225us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 8.110s 3135.266us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 30.070s 2479.366us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.320s 647.110us 1 1 100.00
hmac_test_sha384_vectors 21.680s 245.503us 1 1 100.00
hmac_test_sha512_vectors 413.870s 46058.953us 1 1 100.00
hmac_test_hmac256_vectors 12.750s 1445.957us 1 1 100.00
hmac_test_hmac384_vectors 8.470s 1056.616us 1 1 100.00
hmac_test_hmac512_vectors 8.540s 941.973us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 9.710s 219.908us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 1.870s 51.913us 1 1 100.00
error 1 1 100.00
hmac_error 33.580s 9955.406us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 64.660s 1972.072us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 9.600s 261.450us 1 1 100.00
hmac_long_msg 8.110s 3135.266us 1 1 100.00
hmac_back_pressure 30.070s 2479.366us 1 1 100.00
hmac_datapath_stress 1.870s 51.913us 1 1 100.00
hmac_burst_wr 9.710s 219.908us 1 1 100.00
hmac_stress_all 405.970s 15788.509us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 9.600s 261.450us 1 1 100.00
hmac_long_msg 8.110s 3135.266us 1 1 100.00
hmac_back_pressure 30.070s 2479.366us 1 1 100.00
hmac_datapath_stress 1.870s 51.913us 1 1 100.00
hmac_wipe_secret 64.660s 1972.072us 1 1 100.00
hmac_test_sha256_vectors 8.320s 647.110us 1 1 100.00
hmac_test_sha384_vectors 21.680s 245.503us 1 1 100.00
hmac_test_sha512_vectors 413.870s 46058.953us 1 1 100.00
hmac_test_hmac256_vectors 12.750s 1445.957us 1 1 100.00
hmac_test_hmac384_vectors 8.470s 1056.616us 1 1 100.00
hmac_test_hmac512_vectors 8.540s 941.973us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 9.600s 261.450us 1 1 100.00
hmac_long_msg 8.110s 3135.266us 1 1 100.00
hmac_back_pressure 30.070s 2479.366us 1 1 100.00
hmac_datapath_stress 1.870s 51.913us 1 1 100.00
hmac_burst_wr 9.710s 219.908us 1 1 100.00
hmac_error 33.580s 9955.406us 1 1 100.00
hmac_wipe_secret 64.660s 1972.072us 1 1 100.00
hmac_test_sha256_vectors 8.320s 647.110us 1 1 100.00
hmac_test_sha384_vectors 21.680s 245.503us 1 1 100.00
hmac_test_sha512_vectors 413.870s 46058.953us 1 1 100.00
hmac_test_hmac256_vectors 12.750s 1445.957us 1 1 100.00
hmac_test_hmac384_vectors 8.470s 1056.616us 1 1 100.00
hmac_test_hmac512_vectors 8.540s 941.973us 1 1 100.00
hmac_stress_all 405.970s 15788.509us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 405.970s 15788.509us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.680s 12.720us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.710s 15.932us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.720s 208.284us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.720s 208.284us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.930s 85.640us 1 1 100.00
hmac_csr_rw 1.060s 252.074us 1 1 100.00
hmac_csr_aliasing 4.410s 1039.225us 1 1 100.00
hmac_same_csr_outstanding 1.070s 43.685us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.930s 85.640us 1 1 100.00
hmac_csr_rw 1.060s 252.074us 1 1 100.00
hmac_csr_aliasing 4.410s 1039.225us 1 1 100.00
hmac_same_csr_outstanding 1.070s 43.685us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 3.690s 270.928us 1 1 100.00
hmac_sec_cm 1.430s 472.023us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.690s 270.928us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 9.600s 261.450us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.120s 204.560us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 614.820s 450569.064us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.000s 8.394us 1 1 100.00

Error Messages

   Test seed line log context