i2c Simulation Results

Simulation Results: i2c

11/12/2025 16:10:21 sha: 9c781e9 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.47 %

code
81.51 %

assert
96.19 %

func
81.71 %

line
96.41 %

branch
92.33 %

cond
85.08 %

toggle
89.66 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		87.76%
V2S		100.00%
V3		0.00%

9/9 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	54.330s	13921.437us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	9.800s	5798.361us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.770s	34.012us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.820s	26.976us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	1.840s	64.575us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.050s	257.367us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.780s	84.554us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.820s	26.976us	1	1	100.00
	i2c_csr_aliasing	1.050s	257.367us	1	1	100.00

43/49 passed

87.76 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.090s	269.802us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	302.830s	13649.736us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	30.680s	13466.528us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.690s	46.404us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	72.480s	16975.066us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	45.740s	2383.615us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.920s	145.285us	1	1	100.00
	i2c_host_fifo_fmt_empty	7.860s	1143.763us	1	1	100.00
	i2c_host_fifo_reset_rx	4.540s	134.780us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	36.930s	9087.113us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	19.070s	2740.972us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.820s	101.929us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.870s	2264.214us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	849.380s	51131.181us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.160s	876.522us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	33.650s	1108.552us	1	1	100.00
	i2c_target_intr_smoke	3.590s	3562.051us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.030s	342.016us	1	1	100.00
	i2c_target_fifo_reset_tx	0.800s	360.203us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	4.950s	12453.526us	1	1	100.00
	i2c_target_stress_rd	33.650s	1108.552us	1	1	100.00
	i2c_target_intr_stress_wr	17.130s	15698.790us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.410s	1348.844us	1	1	100.00
target_clock_stretch				0	1	0.00
	i2c_target_stretch	4.070s	10005.215us	0	1	0.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.850s	3555.205us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	3.230s	10090.606us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.340s	521.924us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.150s	628.967us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	30.680s	13466.528us	1	1	100.00
	i2c_host_perf_precise	2.440s	229.410us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	19.070s	2740.972us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.710s	513.963us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.890s	560.032us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.510s	1472.547us	1	1	100.00
	i2c_target_nack_txstretch	1.080s	479.535us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.270s	268.927us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.550s	2054.978us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.670s	21.257us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.710s	52.048us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.070s	25.766us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.070s	25.766us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.770s	34.012us	1	1	100.00
	i2c_csr_rw	0.820s	26.976us	1	1	100.00
	i2c_csr_aliasing	1.050s	257.367us	1	1	100.00
	i2c_same_csr_outstanding	0.950s	48.337us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.770s	34.012us	1	1	100.00
	i2c_csr_rw	0.820s	26.976us	1	1	100.00
	i2c_csr_aliasing	1.050s	257.367us	1	1	100.00
	i2c_same_csr_outstanding	0.950s	48.337us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_sec_cm	0.760s	74.585us	1	1	100.00
	i2c_tl_intg_err	1.710s	129.635us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.710s	129.635us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	10.510s	1124.675us	1
target_error_intr				1
	i2c_target_unexp_stop	1.130s	1252.990us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	10.790s	1247.383us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	61060306770356206866457153324151177497746525439402352783867875777083815612731	83	UVM_ERROR @ 269802066 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 269802066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
	i2c_host_stress_all	92829098720862719641302737234161186927228193136057583393026171880679505767571	123	UVM_ERROR @ 13649735628 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared: ---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @8154713
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	58249565549847797774837147548382919514943020799449020110739933801948611605981	81	UVM_ERROR @ 2264214223 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between UVM_INFO @ 2264214223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
	i2c_target_stretch	59572497246580251990624599695601563304222491750664513564690557088547090878895	75	UVM_FATAL @ 10005215095 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! UVM_INFO @ 10005215095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])
	i2c_target_unexp_stop	47081232590615866927909947905535279712963231815919910351741763466189489093391	75	UVM_ERROR @ 1252989774 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1]) UVM_INFO @ 1252989774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
	i2c_target_hrst	71955090375912701621305358668572132517654028313549662063034922896971824516961	76	UVM_FATAL @ 10090606367 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! UVM_INFO @ 10090606367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	77370613144392769246475170281933568644519296347715261579917622661995284746307	104	UVM_ERROR @ 1124675335 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1124675335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	110857490427151962539027342906901157653375336309444874267963847770635861882411	102	UVM_ERROR @ 1247383327 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1247383327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
	i2c_host_mode_toggle	79578090714349369449657839696948164543003701014455819422579244143743055347552	84	UVM_ERROR @ 101929271 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead --> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------