Simulation Results: keymgr

 
11/12/2025 16:10:21 sha: 9c781e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.32 %
  • code
  • 95.84 %
  • assert
  • 97.49 %
  • func
  • 65.64 %
  • line
  • 98.78 %
  • branch
  • 97.94 %
  • cond
  • 94.16 %
  • toggle
  • 97.64 %
  • FSM
  • 90.70 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.060s 130.194us 1 1 100.00
random 1 1 100.00
keymgr_random 3.430s 117.405us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.360s 35.273us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.040s 19.468us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 5.390s 491.432us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 9.690s 1505.760us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.200s 37.419us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.040s 19.468us 1 1 100.00
keymgr_csr_aliasing 9.690s 1505.760us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 7.200s 821.105us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.170s 49.916us 1 1 100.00
keymgr_sideload_kmac 1.740s 65.736us 1 1 100.00
keymgr_sideload_aes 4.080s 2064.576us 1 1 100.00
keymgr_sideload_otbn 2.950s 164.640us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.780s 30.514us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.510s 299.282us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.440s 687.115us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 3.090s 98.385us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 5.720s 226.384us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.430s 42.882us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 23.020s 1937.794us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.810s 12.843us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.640s 43.105us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.000s 165.080us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.000s 165.080us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.360s 35.273us 1 1 100.00
keymgr_csr_rw 1.040s 19.468us 1 1 100.00
keymgr_csr_aliasing 9.690s 1505.760us 1 1 100.00
keymgr_same_csr_outstanding 2.030s 65.878us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.360s 35.273us 1 1 100.00
keymgr_csr_rw 1.040s 19.468us 1 1 100.00
keymgr_csr_aliasing 9.690s 1505.760us 1 1 100.00
keymgr_same_csr_outstanding 2.030s 65.878us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 11.790s 1570.233us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_tl_intg_err 5.760s 183.690us 1 1 100.00
keymgr_sec_cm 11.790s 1570.233us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 1.520s 171.268us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 1.520s 171.268us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 1.520s 171.268us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 1.520s 171.268us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 11.260s 1719.151us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 11.790s 1570.233us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 11.790s 1570.233us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 5.760s 183.690us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 1.520s 171.268us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 7.200s 821.105us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_csr_rw 1.040s 19.468us 1 1 100.00
keymgr_random 3.430s 117.405us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_csr_rw 1.040s 19.468us 1 1 100.00
keymgr_random 3.430s 117.405us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_csr_rw 1.040s 19.468us 1 1 100.00
keymgr_random 3.430s 117.405us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.510s 299.282us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 5.720s 226.384us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 5.720s 226.384us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 3.430s 117.405us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.930s 66.855us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 11.790s 1570.233us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 11.790s 1570.233us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 11.790s 1570.233us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.820s 288.557us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.510s 299.282us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 11.790s 1570.233us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 11.790s 1570.233us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 11.790s 1570.233us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.820s 288.557us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.820s 288.557us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 11.790s 1570.233us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.820s 288.557us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 11.790s 1570.233us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.820s 288.557us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 3.120s 421.292us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 110422258247669857768798573186611288921247719536669338746974715477825120730065 190
UVM_ERROR @ 421291632 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 421291632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---