Simulation Results: lc_ctrl

 
11/12/2025 16:10:21 sha: 9c781e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.10 %
  • code
  • 87.14 %
  • assert
  • 95.99 %
  • func
  • 84.17 %
  • line
  • 97.53 %
  • branch
  • 95.70 %
  • cond
  • 79.10 %
  • toggle
  • 75.27 %
  • FSM
  • 88.10 %
Validation stages
V1
100.00%
V2
85.00%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 0.940s 19.134us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.930s 50.434us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.140s 16.800us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.650s 571.833us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 198.024us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.110s 103.809us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.140s 16.800us 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 198.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 2.790s 1149.552us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.840s 428.122us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 36.830us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.690s 61.648us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.290s 20.430us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.350s 171.312us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 1.290s 20.430us 0 1 0.00
lc_ctrl_prog_failure 1.690s 61.648us 1 1 100.00
lc_ctrl_errors 4.350s 171.312us 1 1 100.00
lc_ctrl_security_escalation 8.570s 1679.956us 1 1 100.00
lc_ctrl_jtag_state_failure 1.500s 103.197us 0 1 0.00
lc_ctrl_jtag_prog_failure 6.680s 1079.459us 1 1 100.00
lc_ctrl_jtag_errors 38.440s 11335.367us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 5.670s 1518.015us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.450s 1123.445us 0 1 0.00
lc_ctrl_jtag_prog_failure 6.680s 1079.459us 1 1 100.00
lc_ctrl_jtag_errors 38.440s 11335.367us 1 1 100.00
lc_ctrl_jtag_access 1.940s 68.504us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 20.870s 3259.283us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.280s 165.216us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.280s 97.339us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 15.890s 2209.987us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.870s 1310.272us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.140s 19.990us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.010s 473.998us 1 1 100.00
lc_ctrl_jtag_alert_test 0.850s 80.340us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.410s 3242.467us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.020s 51.610us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 13.710s 1724.086us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.120s 117.449us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.940s 61.013us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.940s 61.013us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.930s 50.434us 1 1 100.00
lc_ctrl_csr_rw 1.140s 16.800us 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 198.024us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.420s 79.649us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.930s 50.434us 1 1 100.00
lc_ctrl_csr_rw 1.140s 16.800us 1 1 100.00
lc_ctrl_csr_aliasing 0.970s 198.024us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.420s 79.649us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.460s 1084.321us 1 1 100.00
lc_ctrl_tl_intg_err 1.720s 262.064us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.720s 262.064us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.840s 428.122us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.290s 20.430us 0 1 0.00
lc_ctrl_sec_cm 6.460s 1084.321us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.290s 20.430us 0 1 0.00
lc_ctrl_sec_cm 6.460s 1084.321us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.290s 20.430us 0 1 0.00
lc_ctrl_sec_cm 6.460s 1084.321us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.290s 20.430us 0 1 0.00
lc_ctrl_sec_cm 6.460s 1084.321us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.290s 20.430us 0 1 0.00
lc_ctrl_sec_cm 6.460s 1084.321us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.290s 20.430us 0 1 0.00
lc_ctrl_sec_cm 6.460s 1084.321us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.290s 20.430us 0 1 0.00
lc_ctrl_sec_cm 6.460s 1084.321us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.290s 20.430us 0 1 0.00
lc_ctrl_sec_cm 6.460s 1084.321us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.570s 1679.956us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 2.790s 1149.552us 0 1 0.00
lc_ctrl_jtag_state_post_trans 4.450s 1123.445us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.880s 317.080us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.880s 317.080us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.930s 4904.480us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.190s 1118.546us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.190s 1118.546us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.110s 20.021us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 42013098004555008602934644246714446303534811940715360671067072308670652745567 164
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 20429771 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 20429771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_state_post_trans 23951113718261079937781341324984981699890725553603226643445442902266330185780 499
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1149551954 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1149551954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 36429298025805971274549162753050617767257196305863952919113647846413975406170 191
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 103196741 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 103196741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 14959513377119780132750793297011744398038421434684209901910529207584780775389 363
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1123445267 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1123445267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 2214894110492362759930362290891642753471399411240359320123056521183062354800 461
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1724086399 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1724086399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 62274624321082694491046394253700295534676103894497970306226095700478081157043 410
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 20021427 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 20021427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---