Simulation Results: lc_ctrl

 
11/12/2025 16:10:21 sha: 9c781e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.53 %
  • code
  • 87.65 %
  • assert
  • 95.99 %
  • func
  • 87.95 %
  • line
  • 97.82 %
  • branch
  • 96.43 %
  • cond
  • 79.87 %
  • toggle
  • 82.73 %
  • FSM
  • 81.40 %
Validation stages
V1
100.00%
V2
90.00%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.810s 594.440us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.960s 20.908us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.760s 57.690us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.100s 440.998us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 80.485us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.930s 35.001us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.760s 57.690us 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 80.485us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.810s 161.085us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.170s 1270.238us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.930s 31.599us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.670s 120.424us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.120s 13.315us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.140s 687.365us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 1.120s 13.315us 0 1 0.00
lc_ctrl_prog_failure 2.670s 120.424us 1 1 100.00
lc_ctrl_errors 4.140s 687.365us 1 1 100.00
lc_ctrl_security_escalation 5.340s 630.196us 1 1 100.00
lc_ctrl_jtag_state_failure 4.840s 212.616us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.630s 4147.613us 1 1 100.00
lc_ctrl_jtag_errors 25.650s 2804.860us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 1.960s 1396.382us 1 1 100.00
lc_ctrl_jtag_state_post_trans 1.930s 349.893us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.630s 4147.613us 1 1 100.00
lc_ctrl_jtag_errors 25.650s 2804.860us 1 1 100.00
lc_ctrl_jtag_access 6.420s 3272.286us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.260s 1949.349us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.560s 98.019us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.580s 130.215us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 14.260s 2127.050us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.140s 245.580us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.100s 413.559us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.510s 713.144us 1 1 100.00
lc_ctrl_jtag_alert_test 0.930s 74.712us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 13.180s 1867.060us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.720s 25.340us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 12.520s 2758.764us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.950s 31.287us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.630s 110.518us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.630s 110.518us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 20.908us 1 1 100.00
lc_ctrl_csr_rw 0.760s 57.690us 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 80.485us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 77.930us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 20.908us 1 1 100.00
lc_ctrl_csr_rw 0.760s 57.690us 1 1 100.00
lc_ctrl_csr_aliasing 0.980s 80.485us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 77.930us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.160s 477.141us 1 1 100.00
lc_ctrl_tl_intg_err 1.330s 122.542us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.330s 122.542us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.170s 1270.238us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.120s 13.315us 0 1 0.00
lc_ctrl_sec_cm 5.160s 477.141us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.120s 13.315us 0 1 0.00
lc_ctrl_sec_cm 5.160s 477.141us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.120s 13.315us 0 1 0.00
lc_ctrl_sec_cm 5.160s 477.141us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.120s 13.315us 0 1 0.00
lc_ctrl_sec_cm 5.160s 477.141us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.120s 13.315us 0 1 0.00
lc_ctrl_sec_cm 5.160s 477.141us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.120s 13.315us 0 1 0.00
lc_ctrl_sec_cm 5.160s 477.141us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.120s 13.315us 0 1 0.00
lc_ctrl_sec_cm 5.160s 477.141us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.120s 13.315us 0 1 0.00
lc_ctrl_sec_cm 5.160s 477.141us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.340s 630.196us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 5.810s 161.085us 1 1 100.00
lc_ctrl_jtag_state_post_trans 1.930s 349.893us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.520s 236.158us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.520s 236.158us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.080s 645.022us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.190s 262.816us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.190s 262.816us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 18.680s 6202.613us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 37680055520545658283869729296507499538304537608256559900750901611687891413460 121
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 13315253 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 13315253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 33308499874767341616509424303914117933507102869608242328871834162288622341659 417
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 212616052 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 212616052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 53312313470160229997177737967696670186609778308016444839031805204350409041082 281
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 349892750 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 349892750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 97560851299903876935013650726349101417404480460420827015978068616158379811546 648
UVM_ERROR @ 6202613089 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6202613089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---