otp_ctrl Simulation Results

Simulation Results: otp_ctrl

11/12/2025 16:10:21 sha: 9c781e9 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
74.87 %

code
73.21 %

assert
91.37 %

func
60.04 %

line
87.38 %

branch
82.97 %

cond
85.51 %

toggle
70.77 %

FSM
39.44 %

Validation stages

V1		90.91%
V2		76.00%
V2S		50.00%
V3		0.00%

10/11 passed

90.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	otp_ctrl_wake_up	2.340s	765.935us	1	1	100.00
smoke				1	1	100.00
	otp_ctrl_smoke	7.250s	881.561us	1	1	100.00
csr_hw_reset				1	1	100.00
	otp_ctrl_csr_hw_reset	2.760s	248.932us	1	1	100.00
csr_rw				1	1	100.00
	otp_ctrl_csr_rw	1.640s	76.892us	1	1	100.00
csr_bit_bash				1	1	100.00
	otp_ctrl_csr_bit_bash	3.210s	329.731us	1	1	100.00
csr_aliasing				1	1	100.00
	otp_ctrl_csr_aliasing	5.640s	448.331us	1	1	100.00
csr_mem_rw_with_rand_reset				0	1	0.00
	otp_ctrl_csr_mem_rw_with_rand_reset	1.470s	60.524us	0	1	0.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	otp_ctrl_csr_rw	1.640s	76.892us	1	1	100.00
	otp_ctrl_csr_aliasing	5.640s	448.331us	1	1	100.00
mem_walk				1	1	100.00
	otp_ctrl_mem_walk	1.570s	53.028us	1	1	100.00
mem_partial_access				1	1	100.00
	otp_ctrl_mem_partial_access	1.640s	83.094us	1	1	100.00

19/25 passed

76.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
dai_access_partition_walk				0	1	0.00
	otp_ctrl_partition_walk	111.060s	4968.751us	0	1	0.00
init_fail				1	1	100.00
	otp_ctrl_init_fail	3.740s	305.012us	1	1	100.00
partition_check				2	2	100.00
	otp_ctrl_background_chks	25.450s	2084.651us	1	1	100.00
	otp_ctrl_check_fail	21.030s	1463.565us	1	1	100.00
regwen_during_otp_init				0	1	0.00
	otp_ctrl_regwen	9.710s	400.146us	0	1	0.00
partition_lock				1	1	100.00
	otp_ctrl_dai_lock	5.060s	2604.249us	1	1	100.00
interface_key_check				0	1	0.00
	otp_ctrl_parallel_key_req	7.000s	1274.963us	0	1	0.00
lc_interactions				2	2	100.00
	otp_ctrl_parallel_lc_req	15.180s	1244.455us	1	1	100.00
	otp_ctrl_parallel_lc_esc	8.340s	466.856us	1	1	100.00
otp_dai_errors				0	1	0.00
	otp_ctrl_dai_errs	7.760s	1674.692us	0	1	0.00
otp_macro_errors				0	1	0.00
	otp_ctrl_macro_errs	3.520s	172.942us	0	1	0.00
test_access				0	1	0.00
	otp_ctrl_test_access	50.010s	17574.764us	0	1	0.00
stress_all				1	1	100.00
	otp_ctrl_stress_all	58.300s	12394.488us	1	1	100.00
intr_test				1	1	100.00
	otp_ctrl_intr_test	1.530s	86.164us	1	1	100.00
alert_test				1	1	100.00
	otp_ctrl_alert_test	2.270s	93.740us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	otp_ctrl_tl_errors	2.340s	85.158us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	otp_ctrl_tl_errors	2.340s	85.158us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	otp_ctrl_csr_hw_reset	2.760s	248.932us	1	1	100.00
	otp_ctrl_csr_rw	1.640s	76.892us	1	1	100.00
	otp_ctrl_csr_aliasing	5.640s	448.331us	1	1	100.00
	otp_ctrl_same_csr_outstanding	3.690s	386.977us	1	1	100.00
tl_d_partial_access				4	4	100.00
	otp_ctrl_csr_hw_reset	2.760s	248.932us	1	1	100.00
	otp_ctrl_csr_rw	1.640s	76.892us	1	1	100.00
	otp_ctrl_csr_aliasing	5.640s	448.331us	1	1	100.00
	otp_ctrl_same_csr_outstanding	3.690s	386.977us	1	1	100.00

V2S

28/56 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
tl_intg_err				1	2	50.00
	otp_ctrl_tl_intg_err	43.580s	22212.660us	1	1	100.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
prim_count_check				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
prim_fsm_check				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_bus_integrity				1	1	100.00
	otp_ctrl_tl_intg_err	43.580s	22212.660us	1	1	100.00
sec_cm_secret_mem_scramble				1	1	100.00
	otp_ctrl_smoke	7.250s	881.561us	1	1	100.00
sec_cm_part_mem_digest				1	1	100.00
	otp_ctrl_smoke	7.250s	881.561us	1	1	100.00
sec_cm_dai_fsm_sparse				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_kdi_fsm_sparse				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_lci_fsm_sparse				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_part_fsm_sparse				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_scrmbl_fsm_sparse				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_timer_fsm_sparse				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_dai_ctr_redun				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_kdi_seed_ctr_redun				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_kdi_entropy_ctr_redun				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_lci_ctr_redun				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_part_ctr_redun				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_scrmbl_ctr_redun				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_timer_integ_ctr_redun				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_timer_cnsty_ctr_redun				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_timer_lfsr_redun				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_dai_fsm_local_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	8.340s	466.856us	1	1	100.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_lci_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	8.340s	466.856us	1	1	100.00
sec_cm_kdi_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	8.340s	466.856us	1	1	100.00
sec_cm_part_fsm_local_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	8.340s	466.856us	1	1	100.00
	otp_ctrl_macro_errs	3.520s	172.942us	0	1	0.00
sec_cm_scrmbl_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	8.340s	466.856us	1	1	100.00
sec_cm_timer_fsm_local_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	8.340s	466.856us	1	1	100.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_dai_fsm_global_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	8.340s	466.856us	1	1	100.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_lci_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	8.340s	466.856us	1	1	100.00
sec_cm_kdi_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	8.340s	466.856us	1	1	100.00
sec_cm_part_fsm_global_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	8.340s	466.856us	1	1	100.00
	otp_ctrl_macro_errs	3.520s	172.942us	0	1	0.00
sec_cm_scrmbl_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	8.340s	466.856us	1	1	100.00
sec_cm_timer_fsm_global_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	8.340s	466.856us	1	1	100.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_part_data_reg_integrity				1	1	100.00
	otp_ctrl_init_fail	3.740s	305.012us	1	1	100.00
sec_cm_part_data_reg_bkgn_chk				1	1	100.00
	otp_ctrl_check_fail	21.030s	1463.565us	1	1	100.00
sec_cm_part_mem_regren				1	1	100.00
	otp_ctrl_dai_lock	5.060s	2604.249us	1	1	100.00
sec_cm_part_mem_sw_unreadable				1	1	100.00
	otp_ctrl_dai_lock	5.060s	2604.249us	1	1	100.00
sec_cm_part_mem_sw_unwritable				1	1	100.00
	otp_ctrl_dai_lock	5.060s	2604.249us	1	1	100.00
sec_cm_lc_part_mem_sw_noaccess				1	1	100.00
	otp_ctrl_dai_lock	5.060s	2604.249us	1	1	100.00
sec_cm_access_ctrl_mubi				1	1	100.00
	otp_ctrl_dai_lock	5.060s	2604.249us	1	1	100.00
sec_cm_token_valid_ctrl_mubi				1	1	100.00
	otp_ctrl_smoke	7.250s	881.561us	1	1	100.00
sec_cm_lc_ctrl_intersig_mubi				1	1	100.00
	otp_ctrl_dai_lock	5.060s	2604.249us	1	1	100.00
sec_cm_test_bus_lc_gated				1	1	100.00
	otp_ctrl_smoke	7.250s	881.561us	1	1	100.00
sec_cm_test_tl_lc_gate_fsm_sparse				0	1	0.00
	otp_ctrl_sec_cm	349.090s	200000.000us	0	1	0.00
sec_cm_direct_access_config_regwen				0	1	0.00
	otp_ctrl_regwen	9.710s	400.146us	0	1	0.00
sec_cm_check_trigger_config_regwen				1	1	100.00
	otp_ctrl_smoke	7.250s	881.561us	1	1	100.00
sec_cm_check_config_regwen				1	1	100.00
	otp_ctrl_smoke	7.250s	881.561us	1	1	100.00
sec_cm_macro_mem_integrity				0	1	0.00
	otp_ctrl_macro_errs	3.520s	172.942us	0	1	0.00

0/2 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
otp_ctrl_low_freq_read				1
	otp_ctrl_low_freq_read	122.510s	46540.159us	1
stress_all_with_rand_reset				1
	otp_ctrl_stress_all_with_rand_reset	18.070s	905.082us	1

Error Messages

	Test	seed	line	log context
Offending '(cio_test_en_o == *)'
	otp_ctrl_csr_mem_rw_with_rand_reset	97501424843765191199804815124503363340880698056698172186769255926927672696435	89	Offending '(cio_test_en_o == 0)' UVM_ERROR @ 60524009 ps: (otp_ctrl_if.sv:389) [ASSERT FAILED] CioTestEnOWithDftOff_A UVM_INFO @ 60524009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr ed* rdata* readout mismatch
	otp_ctrl_partition_walk	105820518114376725877848007405154552539918973347275223785660027944593865228271	120484	UVM_ERROR @ 4968750690 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_partition_walk_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 16080 [0x3ed0]) dai addr 3ed0 rdata0 readout mismatch UVM_INFO @ 4968750690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr ed* rdata* readout mismatch
	otp_ctrl_low_freq_read	92111157398926997343145740670422870717035684583723551909877058940888598165089	86	UVM_ERROR @ 46540158760 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch UVM_INFO @ 46540158760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs []) reg name: otp_ctrl_core_reg_block.err_code_
	otp_ctrl_dai_errs	70065668626225370947316476297665442987969619803755594437003377309411209402704	6415	UVM_ERROR @ 1674692299 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22 UVM_INFO @ 1674692299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs []) reg name: otp_ctrl_core_reg_block.direct_access_rdata_
	otp_ctrl_macro_errs	104891098882501384563647847734578708825330172097908658512016043180602802679682	1845	UVM_ERROR @ 172942377 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8208 [0x2010]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0 UVM_INFO @ 172942377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: otp_ctrl_core_reg_block.intr_state
	otp_ctrl_parallel_key_req	25895274453490305090025357075621350761319590487575462930461200215113545052796	3478	UVM_ERROR @ 1274962692 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state UVM_INFO @ 1274962692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_test_access	82715473089327338526958749576196602039935805915583854050017836755844776407352	11122	UVM_ERROR @ 17574763685 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state UVM_INFO @ 17574763685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value:
	otp_ctrl_regwen	2743670572456308486593005193187693296971504240171714106435342672313940391261	10835	UVM_ERROR @ 400146452 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0 UVM_INFO @ 400146452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [] vs []) d_data mismatch when d_error =
	otp_ctrl_stress_all_with_rand_reset	79759827337855794554579966439998960726027995886142441047148084875543170586413	208	UVM_ERROR @ 905082380 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1 UVM_INFO @ 905082380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	otp_ctrl_sec_cm	70574578028794972415554403200233007234156623764794491564659713316315838714776	2602	UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---