Simulation Results: rstmgr

 
11/12/2025 16:10:21 sha: 9c781e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.25 %
  • code
  • 99.42 %
  • assert
  • 97.44 %
  • func
  • 94.88 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.98 %
  • toggle
  • 99.81 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.190s 70.541us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.940s 63.339us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.840s 36.413us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.080s 66.913us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.200s 43.014us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.860s 98.343us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.840s 36.413us 1 1 100.00
rstmgr_csr_aliasing 1.200s 43.014us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.250s 80.593us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.100s 45.332us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.880s 41.682us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.720s 706.931us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.720s 706.931us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.720s 706.931us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.720s 706.931us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 21.490s 3240.915us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.880s 52.152us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.190s 67.030us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.190s 67.030us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.940s 63.339us 1 1 100.00
rstmgr_csr_rw 0.840s 36.413us 1 1 100.00
rstmgr_csr_aliasing 1.200s 43.014us 1 1 100.00
rstmgr_same_csr_outstanding 1.290s 66.738us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.940s 63.339us 1 1 100.00
rstmgr_csr_rw 0.840s 36.413us 1 1 100.00
rstmgr_csr_aliasing 1.200s 43.014us 1 1 100.00
rstmgr_same_csr_outstanding 1.290s 66.738us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_tl_intg_err 4.200s 642.558us 1 1 100.00
rstmgr_sec_cm 34.020s 7189.703us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 34.020s 7189.703us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 34.020s 7189.703us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 4.200s 642.558us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.090s 54.147us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.560s 412.670us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.420s 291.132us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 34.020s 7189.703us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.840s 36.413us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.840s 36.413us 1 1 100.00

Error Messages

   Test seed line log context