Simulation Results: rv_timer

 
11/12/2025 16:10:21 sha: 9c781e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.72 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 87.35 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.650s 86.880us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.550s 14.888us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.520s 13.266us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.550s 1136.539us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.720s 17.344us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.750s 155.407us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.520s 13.266us 1 1 100.00
rv_timer_csr_aliasing 0.720s 17.344us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.720s 151.443us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.300s 3748.809us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 464.260s 411644.546us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 464.260s 411644.546us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.770s 1432.847us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.510s 79.507us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.630s 18.617us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.330s 197.365us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.330s 197.365us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 14.888us 1 1 100.00
rv_timer_csr_rw 0.520s 13.266us 1 1 100.00
rv_timer_csr_aliasing 0.720s 17.344us 1 1 100.00
rv_timer_same_csr_outstanding 0.560s 14.548us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 14.888us 1 1 100.00
rv_timer_csr_rw 0.520s 13.266us 1 1 100.00
rv_timer_csr_aliasing 0.720s 17.344us 1 1 100.00
rv_timer_same_csr_outstanding 0.560s 14.548us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.870s 149.747us 1 1 100.00
rv_timer_tl_intg_err 0.910s 319.887us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.910s 319.887us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.590s 194.716us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.620s 181.060us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 10.050s 2023.235us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 24952458314288768527257410123688554818706688982964446108061768485742849194352 72
UVM_FATAL @ 194715878 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x18e80904) == 0x1
UVM_INFO @ 194715878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 74353439750125046703897922576133876696151798503364885429254976804193080649198 72
UVM_FATAL @ 151443122 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x26dafd04) == 0x1
UVM_INFO @ 151443122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 68820120414951622938322000341137524772188339636960378144381780384272065974589 73
UVM_ERROR @ 181059819 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 181059819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---