Simulation Results: spi_host

 
11/12/2025 16:10:21 sha: 9c781e9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.71 %
  • code
  • 95.02 %
  • assert
  • 95.21 %
  • func
  • 87.92 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 10.000s 988.631us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 46.543us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 29.785us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 105.447us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 26.518us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 85.525us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 29.785us 1 1 100.00
spi_host_csr_aliasing 1.000s 26.518us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 37.422us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 40.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 32.956us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 4.000s 725.721us 1 1 100.00
spi_host_error_cmd 1.000s 57.728us 1 1 100.00
spi_host_event 14.000s 3318.235us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 48.275us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 48.275us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 48.275us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 83.774us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 23.736us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 48.275us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 48.275us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 10.000s 988.631us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 10.000s 988.631us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 3.000s 365.071us 1 1 100.00
spien 1 1 100.00
spi_host_spien 47.000s 19703.879us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 739.000s 150503.685us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 72.660us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 4.000s 725.721us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 94.262us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 32.118us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 126.718us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 126.718us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 46.543us 1 1 100.00
spi_host_csr_rw 1.000s 29.785us 1 1 100.00
spi_host_csr_aliasing 1.000s 26.518us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 52.199us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 46.543us 1 1 100.00
spi_host_csr_rw 1.000s 29.785us 1 1 100.00
spi_host_csr_aliasing 1.000s 26.518us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 52.199us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 2.000s 54.899us 1 1 100.00
spi_host_tl_intg_err 2.000s 163.051us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 163.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 221.000s 41835.308us 1 1 100.00

Error Messages

   Test seed line log context