Simulation Results: sram_ctrl

 
11/12/2025 16:10:21 sha: 9c781e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.15 %
  • code
  • 95.88 %
  • assert
  • 95.69 %
  • func
  • 93.88 %
  • line
  • 99.11 %
  • branch
  • 97.52 %
  • cond
  • 92.04 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.680s 1407.464us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.810s 17.583us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.800s 19.044us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.910s 469.037us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.710s 45.202us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.560s 924.649us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.800s 19.044us 1 1 100.00
sram_ctrl_csr_aliasing 0.710s 45.202us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 125.880s 9247.836us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 68.100s 13329.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 286.310s 7110.420us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 206.490s 9155.698us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 676.300s 13448.869us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 552.600s 11914.834us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 12.740s 8597.710us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 562.220s 102393.276us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 56.970s 1345.970us 1 1 100.00
sram_ctrl_partial_access_b2b 280.840s 71398.994us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 21.700s 733.904us 1 1 100.00
sram_ctrl_throughput_w_partial_write 63.950s 946.768us 1 1 100.00
sram_ctrl_throughput_w_readback 52.990s 2448.633us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 556.890s 25507.124us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.740s 5611.338us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 3002.100s 416587.331us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.900s 82.740us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.760s 229.958us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.760s 229.958us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.810s 17.583us 1 1 100.00
sram_ctrl_csr_rw 0.800s 19.044us 1 1 100.00
sram_ctrl_csr_aliasing 0.710s 45.202us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.970s 29.578us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.810s 17.583us 1 1 100.00
sram_ctrl_csr_rw 0.800s 19.044us 1 1 100.00
sram_ctrl_csr_aliasing 0.710s 45.202us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.970s 29.578us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 33.140s 28257.026us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.870s 2.152us 0 1 0.00
sram_ctrl_tl_intg_err 1.510s 658.622us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.870s 2.152us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.510s 658.622us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 556.890s 25507.124us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 556.890s 25507.124us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.800s 19.044us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 562.220s 102393.276us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 562.220s 102393.276us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 562.220s 102393.276us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 12.740s 8597.710us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.960s 9484.369us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 33.140s 28257.026us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 6.740s 3014.599us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.680s 1407.464us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.680s 1407.464us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 562.220s 102393.276us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.870s 2.152us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 12.740s 8597.710us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.870s 2.152us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.870s 2.152us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.680s 1407.464us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.870s 2.152us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 4.900s 140.909us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 45753516250736421507530735594110341429507345803386874897921972342772407358470 97
UVM_ERROR @ 2151949 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 2151949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---