uart Simulation Results

Simulation Results: uart

11/12/2025 16:10:21 sha: 9c781e9 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
81.16 %

code
95.06 %

assert
97.12 %

func
51.28 %

line
98.86 %

branch
96.50 %

cond
93.58 %

toggle
91.32 %

Validation stages

V1		100.00%
V2		94.12%
V2S		100.00%
V3		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	1.200s	490.965us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.580s	18.575us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	0.610s	81.624us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	1.280s	181.878us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.770s	32.179us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	0.720s	107.893us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	0.610s	81.624us	1	1	100.00
	uart_csr_aliasing	0.770s	32.179us	1	1	100.00

32/34 passed

94.12 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	5.820s	5020.487us	1	1	100.00
parity				2	2	100.00
	uart_smoke	1.200s	490.965us	1	1	100.00
	uart_tx_rx	5.820s	5020.487us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	26.810s	111263.974us	1	1	100.00
	uart_rx_parity_err	30.180s	120690.163us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	5.820s	5020.487us	1	1	100.00
	uart_intr	26.810s	111263.974us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	9.290s	27767.026us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	18.900s	16352.857us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	11.210s	41319.964us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	26.810s	111263.974us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	26.810s	111263.974us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	26.810s	111263.974us	1	1	100.00
perf				1	1	100.00
	uart_perf	84.650s	15726.819us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	1.710s	3192.632us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	1.710s	3192.632us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	1.600s	2202.078us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	12.360s	48405.692us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	2.200s	713.775us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	43.060s	7054.446us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	398.280s	124073.911us	1	1	100.00
stress_all				0	1	0.00
	uart_stress_all	27.940s	49994.000us	0	1	0.00
alert_test				1	1	100.00
	uart_alert_test	0.550s	43.697us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	0.630s	14.196us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	1.330s	101.403us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	1.330s	101.403us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	0.580s	18.575us	1	1	100.00
	uart_csr_rw	0.610s	81.624us	1	1	100.00
	uart_csr_aliasing	0.770s	32.179us	1	1	100.00
	uart_same_csr_outstanding	0.710s	44.566us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	0.580s	18.575us	1	1	100.00
	uart_csr_rw	0.610s	81.624us	1	1	100.00
	uart_csr_aliasing	0.770s	32.179us	1	1	100.00
	uart_same_csr_outstanding	0.710s	44.566us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	0.910s	78.708us	1	1	100.00
	uart_tl_intg_err	1.090s	270.421us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	1.090s	270.421us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	38.810s	1839.400us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [] vs []) check rx_empty fail: uart_rx_clk_pulses = , rx_q.size = *
	uart_noise_filter	58640334737273011844813608887053714217679212652026639974173885475007487351710	73	UVM_ERROR @ 1642471378 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 2056312988 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 2056312988 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 2056312988 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 2200982548 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 28, clk_pulses: 0
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *
	uart_stress_all	75405450645173485761455303618373186846263367436789512902857687666832143264116	73	UVM_ERROR @ 40454902994 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 40454902994 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 41595301414 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0 UVM_ERROR @ 41595343080 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0 UVM_ERROR @ 41596509728 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0