Simulation Results: ac_range_check

 
15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.92 %
  • code
  • 93.16 %
  • assert
  • 97.63 %
  • func
  • 57.98 %
  • block
  • 99.21 %
  • line
  • 99.94 %
  • branch
  • 98.35 %
  • toggle
  • 81.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 30.000s 6028.744us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 39.000s 9227.607us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 23.299us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 3.000s 99.068us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 29.000s 6520.934us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 16.000s 364.648us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 26.144us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 3.000s 99.068us 1 1 100.00
ac_range_check_csr_aliasing 16.000s 364.648us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 3.000s 83.243us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 31.000s 3271.589us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 120.000s 5411.323us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 13.172us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 19.713us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 2.000s 61.652us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 2.000s 61.652us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 23.299us 1 1 100.00
ac_range_check_csr_rw 3.000s 99.068us 1 1 100.00
ac_range_check_csr_aliasing 16.000s 364.648us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 673.421us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 23.299us 1 1 100.00
ac_range_check_csr_rw 3.000s 99.068us 1 1 100.00
ac_range_check_csr_aliasing 16.000s 364.648us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 673.421us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 834.653us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 834.653us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 834.653us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 834.653us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 92.000s 22259.221us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 2.000s 15.329us 1 1 100.00
ac_range_check_tl_intg_err 7.000s 124.101us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 217.000s 1250.221us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 21.000s 1697.926us 1 1 100.00

Error Messages

   Test seed line log context