Simulation Results: aes

 
15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.03 %
  • code
  • 92.21 %
  • assert
  • 98.25 %
  • func
  • 79.64 %
  • block
  • 93.88 %
  • line
  • 95.55 %
  • branch
  • 86.17 %
  • toggle
  • 97.99 %
  • FSM
  • 89.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 63.354us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 153.918us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 97.137us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 81.374us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 346.526us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 98.082us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 97.793us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 81.374us 1 1 100.00
aes_csr_aliasing 2.000s 98.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 153.918us 1 1 100.00
aes_config_error 2.000s 86.020us 1 1 100.00
aes_stress 2.000s 76.718us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 153.918us 1 1 100.00
aes_config_error 2.000s 86.020us 1 1 100.00
aes_stress 2.000s 76.718us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 76.718us 1 1 100.00
aes_b2b 10.000s 237.994us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 76.718us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 153.918us 1 1 100.00
aes_config_error 2.000s 86.020us 1 1 100.00
aes_stress 2.000s 76.718us 1 1 100.00
aes_alert_reset 4.000s 464.593us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 82.916us 1 1 100.00
aes_config_error 2.000s 86.020us 1 1 100.00
aes_alert_reset 4.000s 464.593us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 5.000s 114.866us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 18.000s 340.520us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 464.593us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 76.718us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 76.718us 1 1 100.00
aes_sideload 5.000s 364.047us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 240.125us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 20.000s 1434.164us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 66.178us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 93.954us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 93.954us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 97.137us 1 1 100.00
aes_csr_rw 2.000s 81.374us 1 1 100.00
aes_csr_aliasing 2.000s 98.082us 1 1 100.00
aes_same_csr_outstanding 2.000s 66.360us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 97.137us 1 1 100.00
aes_csr_rw 2.000s 81.374us 1 1 100.00
aes_csr_aliasing 2.000s 98.082us 1 1 100.00
aes_same_csr_outstanding 2.000s 66.360us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 206.000s 10244.529us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 89.407us 1 1 100.00
aes_control_fi 2.000s 79.478us 1 1 100.00
aes_cipher_fi 1.000s 56.512us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 98.829us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 98.829us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 98.829us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 98.829us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 201.181us 1 1 100.00
tl_intg_err 2 2 100.00
aes_tl_intg_err 2.000s 128.777us 1 1 100.00
aes_sec_cm 7.000s 1910.594us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 128.777us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 464.593us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 98.829us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 98.829us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 4.000s 153.918us 1 1 100.00
aes_stress 2.000s 76.718us 1 1 100.00
aes_alert_reset 4.000s 464.593us 1 1 100.00
aes_core_fi 3.000s 131.085us 1 1 100.00
sec_cm_gcm_config_sparse 2 2 100.00
aes_config_error 2.000s 86.020us 1 1 100.00
aes_stress 2.000s 76.718us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 98.829us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 75.393us 1 1 100.00
aes_stress 2.000s 76.718us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 76.718us 1 1 100.00
aes_sideload 5.000s 364.047us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 75.393us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 75.393us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 75.393us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 75.393us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 75.393us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 76.718us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 76.718us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 89.407us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 89.407us 1 1 100.00
aes_control_fi 2.000s 79.478us 1 1 100.00
aes_cipher_fi 1.000s 56.512us 1 1 100.00
aes_ctr_fi 2.000s 54.025us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 89.407us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 89.407us 1 1 100.00
aes_control_fi 2.000s 79.478us 1 1 100.00
aes_cipher_fi 1.000s 56.512us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 56.512us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 89.407us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 89.407us 1 1 100.00
aes_control_fi 2.000s 79.478us 1 1 100.00
aes_ctr_fi 2.000s 54.025us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 89.407us 1 1 100.00
aes_control_fi 2.000s 79.478us 1 1 100.00
aes_cipher_fi 1.000s 56.512us 1 1 100.00
aes_ctr_fi 2.000s 54.025us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 464.593us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 89.407us 1 1 100.00
aes_control_fi 2.000s 79.478us 1 1 100.00
aes_cipher_fi 1.000s 56.512us 1 1 100.00
aes_ctr_fi 2.000s 54.025us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 89.407us 1 1 100.00
aes_control_fi 2.000s 79.478us 1 1 100.00
aes_cipher_fi 1.000s 56.512us 1 1 100.00
aes_ctr_fi 2.000s 54.025us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 89.407us 1 1 100.00
aes_control_fi 2.000s 79.478us 1 1 100.00
aes_ctr_fi 2.000s 54.025us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 89.407us 1 1 100.00
aes_control_fi 2.000s 79.478us 1 1 100.00
aes_cipher_fi 1.000s 56.512us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 17.000s 699.110us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 61922436157844108429216705617669556414099937904953314755493423407904630071386 375
UVM_FATAL @ 699110033 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 699110033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---