Simulation Results: clkmgr

 
15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.71 %
  • code
  • 69.55 %
  • assert
  • 89.26 %
  • func
  • 65.31 %
  • line
  • 82.45 %
  • branch
  • 87.58 %
  • cond
  • 79.12 %
  • toggle
  • 98.58 %
  • FSM
  • 0.00 %
Validation stages
V1
25.00%
V2
47.37%
V2S
52.94%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 2.100s 83.515us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.980s 28.573us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.650s 4.797us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 3.180s 265.536us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.760s 6.247us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.960s 12.969us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.650s 4.797us 0 1 0.00
clkmgr_csr_aliasing 0.760s 6.247us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.280s 50.439us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.330s 60.859us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.120s 18.401us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 2.100s 83.515us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.880s 5.571us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.770s 3.082us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.880s 5.571us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.710s 3.841us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.770s 15.961us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.050s 75.834us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.050s 75.834us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 0.980s 28.573us 1 1 100.00
clkmgr_csr_rw 0.650s 4.797us 0 1 0.00
clkmgr_csr_aliasing 0.760s 6.247us 0 1 0.00
clkmgr_same_csr_outstanding 0.840s 8.878us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 0.980s 28.573us 1 1 100.00
clkmgr_csr_rw 0.650s 4.797us 0 1 0.00
clkmgr_csr_aliasing 0.760s 6.247us 0 1 0.00
clkmgr_same_csr_outstanding 0.840s 8.878us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_tl_intg_err 0.810s 3.768us 0 1 0.00
clkmgr_sec_cm 22.810s 2670.031us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.570s 228.674us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.570s 228.674us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.570s 228.674us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.570s 228.674us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.500s 53.262us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.810s 3.768us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.880s 5.571us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.770s 3.082us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.570s 228.674us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.780s 19.601us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.650s 4.797us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 22.810s 2670.031us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.650s 4.797us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.650s 4.797us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 22.810s 2670.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.830s 1.813us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.070s 6.406us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 27532737783033852195002675125657649943292592839601176616919127665939659494819 72
UVM_ERROR @ 53262258 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 53262258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *
clkmgr_tl_intg_err 24553956554260062924793902649459359000093634496886087694319428298116110739428 72
UVM_ERROR @ 3767524 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 3767524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 48078519872061419223297398791624938677506618325484987363629799864753197163580 73
UVM_ERROR @ 4797291 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 4797291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 62519286111428560620897305484674524618917873343327364239385199886928643938984 72
UVM_ERROR @ 6246964 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 6246964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 98994310334442805338966562726390167650522660075535501547163914043300550458612 73
UVM_ERROR @ 12968854 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 12968854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 67894443131429698367245543097078399520547685958367319395242985295014543161327 72
UVM_ERROR @ 265535580 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0
UVM_INFO @ 265535580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:642) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
clkmgr_same_csr_outstanding 47594368852527864833412820908555584387098880585800844750344909380400508680301 72
UVM_ERROR @ 8878318 ps: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xbcafbae4 read out mismatch
UVM_INFO @ 8878318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_frequency 103185786349643570322973821953585830908712300624478805044262862831296666725366 72
UVM_ERROR @ 5571134 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00
UVM_INFO @ 5571134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 86227799546430839723984262129440549725957675044717151899938415158572958681988 74
UVM_ERROR @ 6405823 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00
UVM_INFO @ 6405823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*
clkmgr_frequency_timeout 68887658994593464566940383076420943892604962730825291099523100971642303058508 75
UVM_ERROR @ 3082269 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00
UVM_INFO @ 3082269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 70557968067620241659796224859902538123388060151304751661252798764964706296879 74
UVM_ERROR @ 3840875 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00
UVM_INFO @ 3840875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed
clkmgr_regwen 19482011650155208709041988958799281542326238522034653079809588579916858008427 71
UVM_ERROR @ 1812978 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed
UVM_INFO @ 1812978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---