Simulation Results: dma

 
15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 81.64 %
  • code
  • 91.82 %
  • assert
  • 95.34 %
  • func
  • 57.75 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 588.368us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 673.599us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 891.742us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 160.361us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 90.425us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 10.000s 1036.438us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 6.000s 1787.337us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 50.979us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 90.425us 1 1 100.00
dma_csr_aliasing 6.000s 1787.337us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 20.000s 6635.178us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 155.000s 62861.531us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 324.000s 127957.270us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 324.000s 127957.270us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 155.000s 62861.531us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 100.000s 49939.261us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 324.000s 127957.270us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 4.000s 218.229us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 42.000s 12360.242us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 16.286us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 25.768us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 162.184us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 162.184us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 160.361us 1 1 100.00
dma_csr_rw 1.000s 90.425us 1 1 100.00
dma_csr_aliasing 6.000s 1787.337us 1 1 100.00
dma_same_csr_outstanding 3.000s 146.215us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 160.361us 1 1 100.00
dma_csr_rw 1.000s 90.425us 1 1 100.00
dma_csr_aliasing 6.000s 1787.337us 1 1 100.00
dma_same_csr_outstanding 3.000s 146.215us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 19.000s 93.308us 1 1 100.00
dma_generic_stress 100.000s 49939.261us 1 1 100.00
dma_handshake_stress 324.000s 127957.270us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 665.144us 1 1 100.00
tl_intg_err 2 2 100.00
dma_sec_cm 1.000s 29.202us 1 1 100.00
dma_tl_intg_err 2.000s 223.928us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 67.000s 3839.953us 1 1 100.00
dma_longer_transfer 2.000s 1278.325us 1 1 100.00
dma_stress_all_with_rand_reset 3.000s 1810.246us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 98763747398630818837451045374267240667606420169931590707909142270666963669799 88
UVM_ERROR @ 1810246027ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1810246027ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---