| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| edn_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| edn_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 0 | 1 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| default | None | None |
File "/nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py", line 88, in <module>
main()
~~~~^^
File "/nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py", line 32, in main
gapi = yaml.load(open(gapi_filepath), Loader=YamlLoader)
~~~~^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: '/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d/ral_input.yml'
ERROR: Could not find EDA API file "/nightly/current_run/scratch/master/edn-sim-vcs/default/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d"
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
|
|
| cover_reg_top | None | None |
Traceback (most recent call last):
File "/nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py", line 88, in <module>
main()
~~~~^^
File "/nightly/current_run/opentitan/hw/dv/tools/ralgen/ralgen.py", line 32, in main
gapi = yaml.load(open(gapi_filepath), Loader=YamlLoader)
~~~~^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: '/nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d/ral_input.yml'
ERROR: Could not find EDA API file "/nightly/current_run/scratch/master/edn-sim-vcs/cover_reg_top/fusesoc-work/generator_cache/lowrisc_dv_edn_env-ral_0.1-7e38a9bb0417a292b449df2f7ece2138debab74e0a30cac8483273f4c68cad1d"
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
|
|
| Job killed most likely because its dependent job failed. | ||||
| edn_tl_errors | 52450870530540317016629585458451322200029056867109906587113740304743222163298 | None | ||
| edn_tl_intg_err | 105785373343824397244696870404494061177663797350768875485131107019050719510710 | None | ||
| edn_intr_test | 10813655025466488229044573103628832772356607916947142910453900411513667434092 | None | ||
| edn_csr_hw_reset | 79827672030205604530764883450670774094329764954465749997178568236768814918370 | None | ||
| edn_csr_rw | 57955595522646919530897069990427420216017745862328134253864251188984946192861 | None | ||
| edn_csr_bit_bash | 72891633629676547076855733491315788247511037711642018817548927618550639090927 | None | ||
| edn_csr_aliasing | 18647651315758780270886875349629783874540235858995428510365149258070620020836 | None | ||
| edn_same_csr_outstanding | 71565219518401597229672078150299644217602563803191321249346889606269069773516 | None | ||
| edn_csr_mem_rw_with_rand_reset | 32229434768904390670314719580505331270682623284532006189823706598701376251547 | None | ||
| edn_smoke | 18616549280096237708225402937435209397340331902430105897385439211559316721733 | None | ||
| edn_regwen | 113295721712121297275568159221244897347940707143377023721932237700597219097273 | None | ||
| edn_genbits | 45590083330881595690672099761833908570083922430319221513483073665134694976351 | None | ||
| edn_stress_all | 62912227157506685502280523678547024695639367532156257062617162743666726071653 | None | ||
| edn_stress_all_with_rand_reset | 24761692233163632927136711945075176573220612989483403413730448395305029177805 | None | ||
| edn_intr | 90881803422946474017819544474143162365477688698147568400778083558731338679869 | None | ||
| edn_alert | 75302140241121964634166090824301898479462005008972431965725606721982985967868 | None | ||
| edn_err | 86634242421217157917258046074154412220565026456836828823846918123026126351130 | None | ||
| edn_disable | 50895207397887401058430824991219472326997464533788050192711366376673875121284 | None | ||
| edn_disable_auto_req_mode | 88640270299285460957170649615992072188562527612875738086185912479131181367554 | None | ||
| edn_sec_cm | 33861646835980244333737162218469129976572631865680999868232339422372987632666 | None | ||
| edn_alert_test | 48481002596073700493483836464243181018732956305263772255937542001436558782261 | None | ||
| edn | None | None | ||
| edn | None | None | ||