Simulation Results: hmac

 
15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.35 %
  • code
  • 98.53 %
  • assert
  • 96.42 %
  • func
  • 43.10 %
  • line
  • 99.68 %
  • branch
  • 99.34 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.630s 765.137us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.780s 20.982us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.820s 29.626us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.170s 1398.146us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.330s 294.432us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.750s 15.846us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.820s 29.626us 1 1 100.00
hmac_csr_aliasing 2.330s 294.432us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 49.630s 10769.122us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 21.100s 2332.402us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.610s 160.069us 1 1 100.00
hmac_test_sha384_vectors 369.660s 36629.140us 1 1 100.00
hmac_test_sha512_vectors 18.770s 444.110us 1 1 100.00
hmac_test_hmac256_vectors 7.260s 901.102us 1 1 100.00
hmac_test_hmac384_vectors 6.440s 2205.511us 1 1 100.00
hmac_test_hmac512_vectors 7.570s 486.635us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 17.960s 3070.951us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 759.710s 29557.506us 1 1 100.00
error 1 1 100.00
hmac_error 15.790s 1589.361us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 67.180s 7258.822us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.630s 765.137us 1 1 100.00
hmac_long_msg 49.630s 10769.122us 1 1 100.00
hmac_back_pressure 21.100s 2332.402us 1 1 100.00
hmac_datapath_stress 759.710s 29557.506us 1 1 100.00
hmac_burst_wr 17.960s 3070.951us 1 1 100.00
hmac_stress_all 133.860s 3781.473us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.630s 765.137us 1 1 100.00
hmac_long_msg 49.630s 10769.122us 1 1 100.00
hmac_back_pressure 21.100s 2332.402us 1 1 100.00
hmac_datapath_stress 759.710s 29557.506us 1 1 100.00
hmac_wipe_secret 67.180s 7258.822us 1 1 100.00
hmac_test_sha256_vectors 7.610s 160.069us 1 1 100.00
hmac_test_sha384_vectors 369.660s 36629.140us 1 1 100.00
hmac_test_sha512_vectors 18.770s 444.110us 1 1 100.00
hmac_test_hmac256_vectors 7.260s 901.102us 1 1 100.00
hmac_test_hmac384_vectors 6.440s 2205.511us 1 1 100.00
hmac_test_hmac512_vectors 7.570s 486.635us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.630s 765.137us 1 1 100.00
hmac_long_msg 49.630s 10769.122us 1 1 100.00
hmac_back_pressure 21.100s 2332.402us 1 1 100.00
hmac_datapath_stress 759.710s 29557.506us 1 1 100.00
hmac_burst_wr 17.960s 3070.951us 1 1 100.00
hmac_error 15.790s 1589.361us 1 1 100.00
hmac_wipe_secret 67.180s 7258.822us 1 1 100.00
hmac_test_sha256_vectors 7.610s 160.069us 1 1 100.00
hmac_test_sha384_vectors 369.660s 36629.140us 1 1 100.00
hmac_test_sha512_vectors 18.770s 444.110us 1 1 100.00
hmac_test_hmac256_vectors 7.260s 901.102us 1 1 100.00
hmac_test_hmac384_vectors 6.440s 2205.511us 1 1 100.00
hmac_test_hmac512_vectors 7.570s 486.635us 1 1 100.00
hmac_stress_all 133.860s 3781.473us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 133.860s 3781.473us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.660s 18.992us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.590s 51.677us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.340s 176.192us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.340s 176.192us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.780s 20.982us 1 1 100.00
hmac_csr_rw 0.820s 29.626us 1 1 100.00
hmac_csr_aliasing 2.330s 294.432us 1 1 100.00
hmac_same_csr_outstanding 1.150s 55.926us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.780s 20.982us 1 1 100.00
hmac_csr_rw 0.820s 29.626us 1 1 100.00
hmac_csr_aliasing 2.330s 294.432us 1 1 100.00
hmac_same_csr_outstanding 1.150s 55.926us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.910s 298.069us 1 1 100.00
hmac_tl_intg_err 1.340s 207.794us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.340s 207.794us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.630s 765.137us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.120s 124.565us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 105.720s 1729.451us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.470s 184.404us 1 1 100.00

Error Messages

   Test seed line log context