i2c Simulation Results

Simulation Results: i2c

15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
84.89 %

code
81.32 %

assert
96.19 %

func
77.17 %

line
96.35 %

branch
92.19 %

cond
84.78 %

toggle
89.24 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		89.80%
V2S		100.00%
V3		0.00%

9/9 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	30.490s	1119.663us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	6.270s	723.406us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.680s	31.998us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.710s	26.053us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.970s	799.872us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.020s	61.790us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.170s	64.374us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.710s	26.053us	1	1	100.00
	i2c_csr_aliasing	1.020s	61.790us	1	1	100.00

44/49 passed

89.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.650s	18.991us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	227.620s	5592.621us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	2.080s	2451.856us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.710s	20.132us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	75.980s	19175.096us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	42.620s	22480.812us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.790s	91.773us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.940s	336.886us	1	1	100.00
	i2c_host_fifo_reset_rx	4.880s	272.327us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	137.380s	11589.066us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	10.280s	1438.408us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.720s	4.123us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.860s	3185.901us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	26.900s	9513.959us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.630s	736.577us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	15.120s	1401.570us	1	1	100.00
	i2c_target_intr_smoke	3.240s	2974.986us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.920s	321.349us	1	1	100.00
	i2c_target_fifo_reset_tx	1.300s	237.216us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	74.660s	27233.563us	1	1	100.00
	i2c_target_stress_rd	15.120s	1401.570us	1	1	100.00
	i2c_target_intr_stress_wr	106.910s	12289.628us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.260s	9406.742us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	6.540s	4205.894us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.260s	3311.191us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	20.280s	10198.367us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.630s	365.361us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.930s	235.052us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	2.080s	2451.856us	1	1	100.00
	i2c_host_perf_precise	5.770s	708.640us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	10.280s	1438.408us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.450s	73.126us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.480s	2150.952us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.810s	1153.554us	1	1	100.00
	i2c_target_nack_txstretch	1.440s	330.960us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	14.040s	2036.099us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.700s	871.510us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.590s	28.338us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.630s	137.298us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.150s	104.683us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.150s	104.683us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.680s	31.998us	1	1	100.00
	i2c_csr_rw	0.710s	26.053us	1	1	100.00
	i2c_csr_aliasing	1.020s	61.790us	1	1	100.00
	i2c_same_csr_outstanding	0.920s	175.023us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.680s	31.998us	1	1	100.00
	i2c_csr_rw	0.710s	26.053us	1	1	100.00
	i2c_csr_aliasing	1.020s	61.790us	1	1	100.00
	i2c_same_csr_outstanding	0.920s	175.023us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.190s	633.371us	1	1	100.00
	i2c_sec_cm	1.000s	63.552us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.190s	633.371us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	16.420s	1006.953us	1
target_error_intr				1
	i2c_target_unexp_stop	1.510s	124.388us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	7.800s	1689.915us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	98085666145195146979139399558348815858174517664811709140952460707784801022690	83	UVM_ERROR @ 18991389 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 18991389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	114044831826845282439370442011043440084339467700206784524012560747184267704152	78	UVM_ERROR @ 4122564 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 4122564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
	i2c_host_stress_all	64970199053148612970871612475723970394735817682767501655355294165148774880560	118	UVM_ERROR @ 5592621009 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared: ---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @6088635
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	70300515541376306759725615350635560182021881585548924761208343647655443422169	81	UVM_ERROR @ 3185900931 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between UVM_INFO @ 3185900931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])
	i2c_target_unexp_stop	103840065122246574862722012780621934188079056908357895579342455883176119075175	75	UVM_ERROR @ 124388422 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1]) UVM_INFO @ 124388422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
	i2c_target_hrst	51857344413564704584063314535618000054741937736883136909431510758962981894586	76	UVM_FATAL @ 10198366662 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! UVM_INFO @ 10198366662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	106496187102800136516535340027405188340346849776288346692853096490677739993368	88	UVM_ERROR @ 1006953332 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1006953332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	51570315701100358238578422920687677096787757246105081475178339696156032623268	83	UVM_ERROR @ 1689914864 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1689914864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---