Simulation Results: kmac

 
15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.53 %
  • code
  • 90.19 %
  • assert
  • 97.83 %
  • func
  • 92.57 %
  • line
  • 98.69 %
  • branch
  • 96.32 %
  • cond
  • 92.66 %
  • toggle
  • 99.89 %
  • FSM
  • 63.38 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 24.780s 1523.481us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.880s 59.130us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.860s 45.259us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 9.980s 288.698us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.660s 252.341us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.370s 532.575us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.860s 45.259us 1 1 100.00
kmac_csr_aliasing 3.660s 252.341us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.800s 39.367us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.010s 53.105us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1895.180s 86606.511us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 777.260s 20465.593us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1440.460s 73683.269us 1 1 100.00
kmac_test_vectors_sha3_256 30.620s 8637.346us 1 1 100.00
kmac_test_vectors_sha3_384 22.020s 1395.622us 1 1 100.00
kmac_test_vectors_sha3_512 15.150s 1181.327us 1 1 100.00
kmac_test_vectors_shake_128 1950.670s 204918.973us 1 1 100.00
kmac_test_vectors_shake_256 280.230s 11383.111us 1 1 100.00
kmac_test_vectors_kmac 3.410s 367.298us 1 1 100.00
kmac_test_vectors_kmac_xof 2.290s 87.804us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 36.390s 2087.045us 1 1 100.00
app 1 1 100.00
kmac_app 172.700s 15445.191us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 277.450s 23302.057us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 30.900s 2168.477us 1 1 100.00
error 1 1 100.00
kmac_error 79.870s 5488.420us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 6.130s 1233.637us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 5.750s 229.524us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 3.600s 82.160us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 1.280s 26.173us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 6.930s 803.530us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.470s 46.795us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 279.030s 17260.162us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.770s 15.090us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.970s 24.633us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 3.090s 166.988us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 3.090s 166.988us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.880s 59.130us 1 1 100.00
kmac_csr_rw 0.860s 45.259us 1 1 100.00
kmac_csr_aliasing 3.660s 252.341us 1 1 100.00
kmac_same_csr_outstanding 1.170s 44.908us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.880s 59.130us 1 1 100.00
kmac_csr_rw 0.860s 45.259us 1 1 100.00
kmac_csr_aliasing 3.660s 252.341us 1 1 100.00
kmac_same_csr_outstanding 1.170s 44.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.430s 42.021us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.430s 42.021us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.430s 42.021us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.430s 42.021us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
kmac_shadow_reg_errors_with_csr_rw 2.670s 226.655us 0 1 0.00
tl_intg_err 2 2 100.00
kmac_tl_intg_err 1.960s 61.542us 1 1 100.00
kmac_sec_cm 82.860s 14560.252us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 1.960s 61.542us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.470s 46.795us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 24.780s 1523.481us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 36.390s 2087.045us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.430s 42.021us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 82.860s 14560.252us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 82.860s 14560.252us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 82.860s 14560.252us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 24.780s 1523.481us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.470s 46.795us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 82.860s 14560.252us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 268.500s 23166.096us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 24.780s 1523.481us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 36.110s 5108.657us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.entropy_period.prescaler reset value: *
kmac_shadow_reg_errors_with_csr_rw 92327720059080391412976427527131309133032253655105301017885464932617148776516 312
UVM_ERROR @ 226654721 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (282 [0x11a] vs 295 [0x127]) Regname: kmac_reg_block.entropy_period.prescaler reset value: 0x0
UVM_INFO @ 226654721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---