| V1 |
|
100.00% |
| V2 |
|
87.50% |
| V2S |
|
67.86% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| lc_ctrl_smoke | 1.260s | 26.989us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_hw_reset | 1.010s | 46.593us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_rw | 1.050s | 253.002us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_bit_bash | 2.210s | 371.203us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_aliasing | 1.060s | 594.520us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_mem_rw_with_rand_reset | 1.250s | 109.418us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| lc_ctrl_csr_rw | 1.050s | 253.002us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 1.060s | 594.520us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| state_post_trans | 0 | 1 | 0.00 | |||
| lc_ctrl_state_post_trans | 3.370s | 184.079us | 0 | 1 | 0.00 | |
| regwen_during_op | 1 | 1 | 100.00 | |||
| lc_ctrl_regwen_during_op | 7.200s | 365.526us | 1 | 1 | 100.00 | |
| rand_wr_claim_transition_if | 1 | 1 | 100.00 | |||
| lc_ctrl_claim_transition_if | 0.850s | 14.255us | 1 | 1 | 100.00 | |
| lc_prog_failure | 1 | 1 | 100.00 | |||
| lc_ctrl_prog_failure | 1.500s | 302.005us | 1 | 1 | 100.00 | |
| lc_state_failure | 0 | 1 | 0.00 | |||
| lc_ctrl_state_failure | 3.010s | 92.364us | 0 | 1 | 0.00 | |
| lc_errors | 1 | 1 | 100.00 | |||
| lc_ctrl_errors | 4.210s | 259.324us | 1 | 1 | 100.00 | |
| security_escalation | 5 | 7 | 71.43 | |||
| lc_ctrl_state_failure | 3.010s | 92.364us | 0 | 1 | 0.00 | |
| lc_ctrl_prog_failure | 1.500s | 302.005us | 1 | 1 | 100.00 | |
| lc_ctrl_errors | 4.210s | 259.324us | 1 | 1 | 100.00 | |
| lc_ctrl_security_escalation | 4.830s | 2084.971us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_state_failure | 1.570s | 89.276us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_prog_failure | 3.040s | 1121.622us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_errors | 31.200s | 33652.953us | 1 | 1 | 100.00 | |
| jtag_access | 13 | 13 | 100.00 | |||
| lc_ctrl_jtag_smoke | 1.570s | 78.633us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_state_post_trans | 14.410s | 2137.501us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_prog_failure | 3.040s | 1121.622us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_errors | 31.200s | 33652.953us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_access | 2.790s | 1361.416us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_regwen_during_op | 14.670s | 1456.476us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_hw_reset | 2.260s | 581.804us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_rw | 1.550s | 241.090us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_bit_bash | 5.010s | 535.639us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_aliasing | 4.230s | 447.067us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_same_csr_outstanding | 1.550s | 41.136us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 2.690s | 291.606us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_alert_test | 1.370s | 49.878us | 1 | 1 | 100.00 | |
| jtag_priority | 1 | 1 | 100.00 | |||
| lc_ctrl_jtag_priority | 2.730s | 1458.876us | 1 | 1 | 100.00 | |
| lc_ctrl_volatile_unlock | 1 | 1 | 100.00 | |||
| lc_ctrl_volatile_unlock_smoke | 0.810s | 18.034us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| lc_ctrl_stress_all | 21.810s | 944.349us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| lc_ctrl_alert_test | 1.140s | 104.450us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_errors | 2.190s | 44.877us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_errors | 2.190s | 44.877us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| lc_ctrl_csr_hw_reset | 1.010s | 46.593us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_rw | 1.050s | 253.002us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 1.060s | 594.520us | 1 | 1 | 100.00 | |
| lc_ctrl_same_csr_outstanding | 1.180s | 101.466us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| lc_ctrl_csr_hw_reset | 1.010s | 46.593us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_rw | 1.050s | 253.002us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 1.060s | 594.520us | 1 | 1 | 100.00 | |
| lc_ctrl_same_csr_outstanding | 1.180s | 101.466us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| lc_ctrl_sec_cm | 8.250s | 320.091us | 1 | 1 | 100.00 | |
| lc_ctrl_tl_intg_err | 1.330s | 47.237us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_intg_err | 1.330s | 47.237us | 1 | 1 | 100.00 | |
| sec_cm_transition_config_regwen | 1 | 1 | 100.00 | |||
| lc_ctrl_regwen_during_op | 7.200s | 365.526us | 1 | 1 | 100.00 | |
| sec_cm_manuf_state_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 3.010s | 92.364us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 8.250s | 320.091us | 1 | 1 | 100.00 | |
| sec_cm_transition_ctr_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 3.010s | 92.364us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 8.250s | 320.091us | 1 | 1 | 100.00 | |
| sec_cm_manuf_state_bkgn_chk | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 3.010s | 92.364us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 8.250s | 320.091us | 1 | 1 | 100.00 | |
| sec_cm_transition_ctr_bkgn_chk | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 3.010s | 92.364us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 8.250s | 320.091us | 1 | 1 | 100.00 | |
| sec_cm_state_config_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 3.010s | 92.364us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 8.250s | 320.091us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 3.010s | 92.364us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 8.250s | 320.091us | 1 | 1 | 100.00 | |
| sec_cm_kmac_fsm_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 3.010s | 92.364us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 8.250s | 320.091us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_local_esc | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 3.010s | 92.364us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 8.250s | 320.091us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_global_esc | 1 | 1 | 100.00 | |||
| lc_ctrl_security_escalation | 4.830s | 2084.971us | 1 | 1 | 100.00 | |
| sec_cm_main_ctrl_flow_consistency | 1 | 2 | 50.00 | |||
| lc_ctrl_state_post_trans | 3.370s | 184.079us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_state_post_trans | 14.410s | 2137.501us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_mubi | 8.630s | 1703.042us | 1 | 1 | 100.00 | |
| sec_cm_token_valid_ctrl_mubi | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_mubi | 8.630s | 1703.042us | 1 | 1 | 100.00 | |
| sec_cm_token_digest | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_digest | 5.770s | 541.411us | 1 | 1 | 100.00 | |
| sec_cm_token_mux_ctrl_redun | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_mux | 5.620s | 248.752us | 1 | 1 | 100.00 | |
| sec_cm_token_valid_mux_redun | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_mux | 5.620s | 248.752us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| lc_ctrl_stress_all_with_rand_reset | 5.010s | 832.465us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' | ||||
| lc_ctrl_state_failure | 42962979740934145762810769014649409293659822312549847829311348011747589943067 | 434 |
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 92363877 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 92363877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| lc_ctrl_state_post_trans | 86133208615856462497750330399064861270210942764018599795936365051985574722309 | 299 |
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 184078981 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 184078981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| lc_ctrl_jtag_state_failure | 42504935726032805974154152502828068974598288309365172119559257276910106330860 | 279 |
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 89275797 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 89275797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| lc_ctrl_stress_all | 51716723057723465727472247545736647606755928930855544829437896612840415816554 | 1537 |
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 944348614 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 944348614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| lc_ctrl_stress_all_with_rand_reset | 5229567276570816192585614890791664391587082843743052800489401052219476964003 | 507 |
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 832464939 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 832464939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|