Simulation Results: lc_ctrl

 
15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.50 %
  • code
  • 86.30 %
  • assert
  • 95.99 %
  • func
  • 89.21 %
  • line
  • 97.66 %
  • branch
  • 96.43 %
  • cond
  • 79.31 %
  • toggle
  • 83.70 %
  • FSM
  • 74.42 %
Validation stages
V1
100.00%
V2
92.50%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.270s 25.209us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.990s 15.411us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.970s 23.868us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.390s 44.697us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 142.880us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.080s 22.460us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.970s 23.868us 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 142.880us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.840s 76.540us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.490s 1298.907us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.830s 14.297us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.050s 366.578us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 5.420s 81.340us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.740s 412.687us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 5.420s 81.340us 0 1 0.00
lc_ctrl_prog_failure 2.050s 366.578us 1 1 100.00
lc_ctrl_errors 5.740s 412.687us 1 1 100.00
lc_ctrl_security_escalation 4.170s 1061.432us 1 1 100.00
lc_ctrl_jtag_state_failure 2.390s 124.976us 0 1 0.00
lc_ctrl_jtag_prog_failure 8.630s 970.122us 1 1 100.00
lc_ctrl_jtag_errors 25.110s 26116.667us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 1.550s 789.661us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.060s 38.270us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 17.470s 1984.887us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.380s 284.523us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.380s 22.786us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.570s 57.993us 1 1 100.00
lc_ctrl_jtag_alert_test 1.390s 59.648us 1 1 100.00
lc_ctrl_jtag_smoke 2.760s 273.854us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.560s 974.703us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.630s 970.122us 1 1 100.00
lc_ctrl_jtag_errors 25.110s 26116.667us 1 1 100.00
lc_ctrl_jtag_access 5.520s 521.336us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 25.120s 1048.804us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 32.090s 4402.975us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.890s 38.411us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 140.140s 14125.997us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.230s 23.450us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.750s 58.972us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.750s 58.972us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.990s 15.411us 1 1 100.00
lc_ctrl_csr_rw 0.970s 23.868us 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 142.880us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.880s 166.609us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.990s 15.411us 1 1 100.00
lc_ctrl_csr_rw 0.970s 23.868us 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 142.880us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.880s 166.609us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.700s 204.897us 1 1 100.00
lc_ctrl_sec_cm 7.430s 900.787us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.700s 204.897us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.490s 1298.907us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 5.420s 81.340us 0 1 0.00
lc_ctrl_sec_cm 7.430s 900.787us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 5.420s 81.340us 0 1 0.00
lc_ctrl_sec_cm 7.430s 900.787us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.420s 81.340us 0 1 0.00
lc_ctrl_sec_cm 7.430s 900.787us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.420s 81.340us 0 1 0.00
lc_ctrl_sec_cm 7.430s 900.787us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 5.420s 81.340us 0 1 0.00
lc_ctrl_sec_cm 7.430s 900.787us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.420s 81.340us 0 1 0.00
lc_ctrl_sec_cm 7.430s 900.787us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.420s 81.340us 0 1 0.00
lc_ctrl_sec_cm 7.430s 900.787us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 5.420s 81.340us 0 1 0.00
lc_ctrl_sec_cm 7.430s 900.787us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.170s 1061.432us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.840s 76.540us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.560s 974.703us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.960s 399.048us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.960s 399.048us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.630s 3933.594us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.030s 351.720us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.030s 351.720us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 19.360s 1543.626us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 15038781880672496812645835581322496352074446764678370282907095933365780480950 1105
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 81340010 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 81340010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 26548375573347525663727682771907542179743852198979045808265833866095734668251 372
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 124976078 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 124976078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 100266084827499441165953866918089772830344366537860029506976819912876439390034 4463
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1543625749 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1543625749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---