Simulation Results: mbx

 
15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.32 %
  • code
  • 91.50 %
  • assert
  • 96.91 %
  • func
  • 85.55 %
  • block
  • 96.75 %
  • line
  • 96.71 %
  • branch
  • 92.07 %
  • toggle
  • 85.73 %
Validation stages
V1
100.00%
V2
87.50%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 37.000s 12558.298us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 24.501us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 14.242us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 67.878us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 47.008us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
mbx_csr_mem_rw_with_rand_reset 2.000s 25.907us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 14.242us 1 1 100.00
mbx_csr_aliasing 2.000s 47.008us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 10.000s 872.613us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 5.000s 861.100us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 22.000s 4775.441us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 9.000s 2969.959us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 23.350us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 28.291us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
mbx_tl_errors 3.000s 240.519us 1 1 100.00
tl_d_illegal_access 1 1 100.00
mbx_tl_errors 3.000s 240.519us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 24.501us 1 1 100.00
mbx_csr_rw 1.000s 14.242us 1 1 100.00
mbx_csr_aliasing 2.000s 47.008us 1 1 100.00
mbx_same_csr_outstanding 1.000s 88.598us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 24.501us 1 1 100.00
mbx_csr_rw 1.000s 14.242us 1 1 100.00
mbx_csr_aliasing 2.000s 47.008us 1 1 100.00
mbx_same_csr_outstanding 1.000s 88.598us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_sec_cm 1.000s 30.348us 1 1 100.00
mbx_tl_intg_err 3.000s 305.912us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched
mbx_stress 56462979375465313650961169648519220054548213651916351638018101788618199616534 354
UVM_ERROR @ 872613251 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (1128909456 [0x4349ca90] vs 0 [0x0]) RDATA read data mismatched
UVM_INFO @ 872613251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_stress_zero_delays 37620647847952480527004894595033593712513690612824459879665222036500235820832 372
UVM_ERROR @ 861099850 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 527750401 [0x1f74d501]) RDATA read data mismatched
UVM_INFO @ 861099850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---