Simulation Results: otbn

 
15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.30 %
  • code
  • 95.59 %
  • assert
  • 88.59 %
  • func
  • 98.72 %
  • block
  • 99.44 %
  • line
  • 99.57 %
  • branch
  • 93.52 %
  • toggle
  • 91.83 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 92.233us 1 1 100.00
single_binary 1 1 100.00
otbn_single 5.000s 19.871us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 91.372us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 128.582us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 304.853us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 5.000s 22.436us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 32.902us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 128.582us 1 1 100.00
otbn_csr_aliasing 5.000s 22.436us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 31.000s 1392.540us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 10.000s 1874.136us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 24.000s 555.564us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 39.000s 568.796us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 140.000s 451.308us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 44.000s 200.348us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 9.000s 35.140us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 30.155us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 39.905us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 29.044us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 20.549us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 76.701us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 76.701us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 91.372us 1 1 100.00
otbn_csr_rw 3.000s 128.582us 1 1 100.00
otbn_csr_aliasing 5.000s 22.436us 1 1 100.00
otbn_same_csr_outstanding 3.000s 26.703us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 91.372us 1 1 100.00
otbn_csr_rw 3.000s 128.582us 1 1 100.00
otbn_csr_aliasing 5.000s 22.436us 1 1 100.00
otbn_same_csr_outstanding 3.000s 26.703us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 20.397us 1 1 100.00
otbn_dmem_err 10.000s 68.790us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 8.000s 24.769us 1 1 100.00
otbn_controller_ispr_rdata_err 6.000s 103.199us 1 1 100.00
otbn_mac_bignum_acc_err 10.000s 37.187us 1 1 100.00
otbn_urnd_err 6.000s 49.810us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 17.502us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 42.943us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 3.000s 38.869us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_tl_intg_err 15.000s 388.882us 1 1 100.00
otbn_sec_cm 80.000s 1750.599us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 12.000s 562.909us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 80.000s 1750.599us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 80.000s 1750.599us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 92.233us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 10.000s 68.790us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 20.397us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 15.000s 388.882us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 35.140us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 20.397us 1 1 100.00
otbn_dmem_err 10.000s 68.790us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 30.155us 1 1 100.00
otbn_illegal_mem_acc 5.000s 17.502us 1 1 100.00
otbn_sec_cm 80.000s 1750.599us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 80.000s 1750.599us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 5.000s 19.871us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 20.397us 1 1 100.00
otbn_dmem_err 10.000s 68.790us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 30.155us 1 1 100.00
otbn_illegal_mem_acc 5.000s 17.502us 1 1 100.00
otbn_sec_cm 80.000s 1750.599us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 80.000s 1750.599us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 35.140us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 20.397us 1 1 100.00
otbn_dmem_err 10.000s 68.790us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 30.155us 1 1 100.00
otbn_illegal_mem_acc 5.000s 17.502us 1 1 100.00
otbn_sec_cm 80.000s 1750.599us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 80.000s 1750.599us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 5.000s 19.871us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 14.036us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 13.227us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 28.000s 3513.914us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 28.000s 3513.914us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 41.278us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 80.000s 1750.599us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 80.000s 1750.599us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 64.454us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 80.000s 1750.599us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 80.000s 1750.599us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 23.101us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 23.101us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 17.398us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 5.000s 19.871us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 5.000s 19.871us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 5.000s 19.871us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 140.000s 451.308us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 5.000s 19.871us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 5.000s 19.871us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 78.916us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 5.000s 19.871us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 80.000s 1750.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 51.000s 184.805us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_stress_all_with_rand_reset 49514943313710744930665655269093690952785564503281739859979647935070037970330 202
UVM_FATAL @ 184804560 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 184804560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---