Simulation Results: otp_ctrl

 
15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 67.36 %
  • code
  • 67.18 %
  • assert
  • 88.82 %
  • func
  • 46.08 %
  • line
  • 86.72 %
  • branch
  • 81.57 %
  • cond
  • 83.93 %
  • toggle
  • 49.81 %
  • FSM
  • 33.86 %
Validation stages
V1
100.00%
V2
60.00%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.850s 806.839us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 9.510s 529.215us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.670s 115.771us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.140s 610.346us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 6.890s 478.985us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.680s 86.096us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.110s 298.953us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.140s 610.346us 1 1 100.00
otp_ctrl_csr_aliasing 3.680s 86.096us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.420s 45.479us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.200s 40.752us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 164.240s 81066.837us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.360s 673.919us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 5.590s 2077.301us 0 1 0.00
otp_ctrl_check_fail 5.730s 1323.355us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 3.200s 198.874us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 11.510s 592.462us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 4.660s 1794.082us 0 1 0.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 10.330s 577.234us 0 1 0.00
otp_ctrl_parallel_lc_esc 9.520s 1161.980us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 24.530s 1918.576us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 15.910s 1863.314us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 10.160s 723.724us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 4.290s 719.726us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.460s 47.532us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.470s 106.444us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.790s 300.078us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.790s 300.078us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.670s 115.771us 1 1 100.00
otp_ctrl_csr_rw 2.140s 610.346us 1 1 100.00
otp_ctrl_csr_aliasing 3.680s 86.096us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.290s 207.541us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.670s 115.771us 1 1 100.00
otp_ctrl_csr_rw 2.140s 610.346us 1 1 100.00
otp_ctrl_csr_aliasing 3.680s 86.096us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.290s 207.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_tl_intg_err 21.710s 2929.287us 1 1 100.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 21.710s 2929.287us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 9.510s 529.215us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 9.510s 529.215us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 9.520s 1161.980us 1 1 100.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 9.520s 1161.980us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 9.520s 1161.980us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 9.520s 1161.980us 1 1 100.00
otp_ctrl_macro_errs 15.910s 1863.314us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 9.520s 1161.980us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 9.520s 1161.980us 1 1 100.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 9.520s 1161.980us 1 1 100.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 9.520s 1161.980us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 9.520s 1161.980us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 9.520s 1161.980us 1 1 100.00
otp_ctrl_macro_errs 15.910s 1863.314us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 9.520s 1161.980us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 9.520s 1161.980us 1 1 100.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.360s 673.919us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 5.730s 1323.355us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 11.510s 592.462us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 11.510s 592.462us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 11.510s 592.462us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 11.510s 592.462us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 11.510s 592.462us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 9.510s 529.215us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 11.510s 592.462us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 9.510s 529.215us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 239.230s 124756.675us 0 1 0.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 3.200s 198.874us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 9.510s 529.215us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 9.510s 529.215us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 15.910s 1863.314us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 72.430s 21876.955us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.680s 54.432us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_partition_walk 56343535694343660974840983582707590138037704948590640112017335298652175560761 120824
UVM_ERROR @ 81066837080 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_partition_walk_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 16080 [0x3ed0]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 81066837080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 43305913326803401722595023265032937336474500099073976350715614181017893857185 86
UVM_ERROR @ 21876954597 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 21876954597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_background_chks 111691131101097764851152710982992937903370127091420214321946366506124491085651 1459
UVM_ERROR @ 2077301072 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 2077301072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 77056077131452557128992017087687949002014656438997184594229473931697812763001 3632
UVM_ERROR @ 1323354845 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 1323354845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 102134051772675467037596983107348966104279691928670190238855863817395455642876 2117
UVM_ERROR @ 1794082318 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 1794082318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 109004032189351992326104428866929389263392911702693459992511872414001608538712 6916
UVM_ERROR @ 723724390 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 723724390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 110414278703898257255848270554283816263638945773896597853171880097768409479538 2628
UVM_ERROR @ 719726088 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 719726088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask *
otp_ctrl_parallel_lc_req 83076094141897985848208657870868501626186234860551669877381169205136751682105 7974
UVM_ERROR @ 577234230 ps: (otp_ctrl_scoreboard.sv:958) [uvm_test_top.env.scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (258 [0x102] vs 256 [0x100]) reg name: status, compare_mask 0
UVM_INFO @ 577234230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 109167755525261137305822206780027165546449591204102090500060817013872814524215 8906
UVM_ERROR @ 592462173 ps: (otp_ctrl_scoreboard.sv:958) [uvm_test_top.env.scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (259 [0x103] vs 257 [0x101]) reg name: status, compare_mask 0
UVM_INFO @ 592462173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_macro_errs 95792656412523280916952262073700459005011234587691792911740998651048559125064 4774
UVM_ERROR @ 1863314106 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 192 [0xc0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1863314106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *
otp_ctrl_regwen 84192249495584560876448100296852446549076801214782520521472875819085593790843 1433
UVM_ERROR @ 198873908 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 198873908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 95096269378236414157267338000895064588973521620931602287253863264948877773293 88
UVM_ERROR @ 54431717 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 54431717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
otp_ctrl_sec_cm 55624611650395731471185793472985481295593736744405600014118594717858196564028 1577
UVM_ERROR @ 124756675030 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
UVM_INFO @ 124756675030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---